JP3198141B2 - Method for manufacturing semiconductor nonvolatile memory element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor nonvolatile memory element, and more particularly to a method of manufacturing a semiconductor nonvolatile memory element capable of achieving high integration.

[0002]

2. Description of the Related Art Generally, since a MOS transistor is required for rewriting and reading information from a nonvolatile memory element, a MOS transistor and a memory transistor are formed in the same element region. In the manufacturing process of the non-volatile memory element, a method of forming a MOS gate electrode of a MOS transistor and a memory gate electrode of a memory transistor includes a gate electrode forming step described below.

A MOS transistor is provided on both sides of a common source in a conventional example.
The manufacturing process of the nonvolatile memory element when forming the gate electrode and the memory gate electrode will be described with reference to the cross-sectional views of FIGS.

First, as shown in FIG. 6, a field oxide film 10 is formed in a field region 15 of a semiconductor substrate 9 of a first conductivity type by using a selective oxidation method. Next, the element region 14
Then, a gate oxide film 20 is formed, and a first polycrystalline silicon film 21 is formed.

Next, as shown in FIG. 7, a resist 16 is formed, and the first polycrystalline silicon film 21 and the gate oxide film 20 are etched using the resist 16 as a mask. A MOS gate electrode 22 made of a polycrystalline silicon film 21 is formed.

Thereafter, as shown in FIG. 8, a memory oxide film 5, a nitride film 6, and a top oxide film 7 obtained by oxidizing the nitride film 6 are formed on the entire surface, and a second polysilicon film is formed on the entire surface. A crystalline silicon film 23 is formed. Then the second
A resist 16 is formed on the polycrystalline silicon film 23 of FIG.

Next, as shown in FIG. 9, the memory gate electrode 1 made of the second polycrystalline silicon film 23 is formed using the resist 16 formed so as to overlap the MOS gate electrode 22 by a photoetching technique as a mask. . Next, M
Using the OS gate electrode 22 and the memory gate electrode 1 as a mask, a second conductivity type high-concentration impurity layer 11 serving as a source and a drain is formed on the semiconductor substrate 9, and a nonvolatile memory element including a memory transistor and a MOS transistor is formed. Form. At this time, the high concentration impurity layer 11 between the two MOS gate electrodes 22 becomes the common source 24.

[0008]

In this conventional semiconductor nonvolatile memory element, high integration is difficult because MOS transistors and memory transistors are mixed. Also, MO
A common source 24 composed of the high-concentration impurity layer 11 is formed between the S gate electrodes 22. Since the common source 24 is a diffusion layer formed in the semiconductor substrate 9, it becomes high resistance when miniaturized, resulting in high integration. Disadvantages arise.

An object of the present invention is to solve the above-mentioned problems and to provide a method of manufacturing a semiconductor nonvolatile memory element which enables high integration.

[0010]

In order to achieve the above object, the present invention employs the following method for manufacturing a nonvolatile semiconductor memory device.

According to a method of manufacturing a semiconductor nonvolatile memory element of the present invention, a field oxide film is formed in a field region around an element region of a semiconductor substrate of a first conductivity type, and a polycrystalline silicon film and a metal silicide film are formed over the entire surface. Forming a common source by a photo-etching technique, and forming a three-layer insulating film including a memory oxide film, a nitride film, and a top oxide film, and forming a polysilicon film on the entire surface. Etching the polysilicon film by an isotropic dry etching technique to form memory gate electrodes on both side walls of the common source; and forming a high-concentration impurity layer in the element region in a region aligned with the memory gate electrode. Forming a high melting point metal film over the entire surface, performing heat treatment, and reacting the silicon of the high concentration impurity layer with the high melting point metal film; Reacting the polysilicon film of the memory gate electrode with the refractory metal film to form a silicide film, removing the unreacted refractory metal film, and forming a multi-layer wiring mainly composed of a silicon dioxide film. Forming a contact window in the insulating film for multi-layer wiring by a photo-etching technique, and forming a wiring metal.

According to a method of manufacturing a semiconductor nonvolatile memory element of the present invention, a field oxide film is formed in a field region around an element region of a semiconductor substrate of a first conductivity type, and a polycrystalline silicon film and a metal silicide film are formed over the entire surface. Forming a common source by a photo-etching technique, and forming a three-layer insulating film including a memory oxide film, a nitride film, and a top oxide film, and forming a polysilicon film on the entire surface. Etching the polysilicon film by an isotropic dry etching technique to form memory gate electrodes on both side walls of the common source; and forming a high-concentration impurity layer in the element region in a region aligned with the memory gate electrode. Forming, a step of forming an insulating film for multilayer wiring mainly composed of a silicon dioxide film, and forming the insulating film for multilayer wiring by photoetching technology. And having a step of forming a Ntakuto windows, and forming a wiring metal.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

First, the structure of the semiconductor nonvolatile memory element according to the present invention will be described with reference to FIG.

Metal silicide film 2 and polycrystalline silicon film 3
Is provided. The memory gate electrodes 1 are provided on both sides of the side wall of the common source 4. A high-concentration impurity layer 11 serving as a drain is provided on the semiconductor substrate 9 in a region where the common source 4 and the memory gate electrode 1 match. Further, a diffusion layer 12 connecting the common source 4 and the semiconductor substrate 9 is formed on the semiconductor substrate 9 below the common source 4.
Is provided. The common source 4 may be only the polycrystalline silicon film 3.

In the nonvolatile memory element thus configured, the common source 4 includes the polycrystalline silicon film 3,
Alternatively, since it is composed of a laminated film of the metal silicide 2 and the polycrystalline silicon film 3, the resistance can be made lower than that of a common source formed on a conventional semiconductor substrate, and miniaturization is possible.

Further, since the memory insulating film of the nonvolatile memory element configured as described above is composed of a three-layer film of the memory oxide film 5, the nitride film 6, and the top oxide film 7,
The memory characteristics are exhibited by the charges trapped in the nitride film 6.

Therefore, the band gap of the silicon oxide film forming the memory oxide film 5 and the top oxide film 7 is larger than the band gap of the nitride film 6. Therefore, the silicon oxide film serving as the memory oxide film 5 and the top oxide film 7 acts as a barrier against electrons and holes when viewed from the nitride film 6.

Therefore, by applying a read voltage which does not cause writing to the memory gate electrode 1 to read data, a MOS transistor which is conventionally required is obtained.
Since a gate electrode is not required, high integration can be achieved.

That is, the method of writing information in the semiconductor nonvolatile memory element of the present invention is performed by setting the writing voltage sufficiently higher than the information reading voltage.

Next, a manufacturing method for forming this structure will be described. 2 to 5 are sectional views showing a manufacturing method for manufacturing the structure of the nonvolatile memory element of the present invention in the order of steps.

First, as shown in FIG. 2, by selectively oxidizing a field region 15 around an element region 14 of a P-type semiconductor substrate 9 of a first conductivity type, a field oxide film 10 having a thickness of 700 nm is formed. It is formed with a thickness.

Next, a polycrystalline silicon film 3 containing a high concentration of phosphorus (P) is formed to a thickness of about 300 nm on the entire surface by a chemical vapor deposition method (hereinafter, referred to as a CVD method) in a monosilane atmosphere. . Further, a metal silicide film 2 made of a tungsten silicide film is formed on the polycrystalline silicon film 3 to a thickness of about 200 nm by a sputtering method.

Next, a resist 16 is formed in a region where the common source 4 is to be formed. Thereafter, the metal silicide film 2 and the polycrystalline silicon film are formed by dry etching using the resist 16 as an etching mask and a mixed gas of sulfur hexafluoride (SF ₆ ) and oxygen (O ₂ ) as an etching gas. 3 is etched. As a result, a common source 4 composed of the metal silicide film 2 and the polycrystalline silicon film 3 is formed.
To form

Next, as shown in FIG. 3, an oxidation process is performed in a mixed gas of oxygen and nitrogen to form a memory oxide film 5 made of a silicon dioxide film having a thickness of about 2 nm. A diffusion layer 12 is formed on the semiconductor substrate 9 by the oxidation process for forming the memory oxide film 5. The diffusion layer 12 is formed by diffusing impurities from the polycrystalline silicon film 3 containing phosphorus at a high concentration into the semiconductor substrate 9.

Next, CV is applied on the entire surface of the memory oxide film 5.
By the method D, a nitride film 6 made of a silicon nitride film is formed with a thickness of about 9 nm.

Further, an oxidation treatment is performed in an oxidizing atmosphere to oxidize the nitride film 6 and form a top oxide film 7 on the nitride film 6.

Next, a polysilicon film 17 is formed to a thickness of about 400 nm over the entire surface by CVD in a monosilane atmosphere.

Next, as shown in FIG. 4, a polysilicon film 17, a top oxide film 7, a nitride film and a nitride film are formed by anisotropic dry etching using a mixed gas of SF ₆ and O ₂ as an etching gas. 6 and the memory oxide film 5 are etched.

As a result, on both sides of the side wall of the common source 4,
The memory gate electrode 1 made of the polysilicon film 17 is formed.

Next, the common source 4 and the memory gate electrode 1
3. As a mask, arsenic is accelerated at an acceleration energy of 60 keV.
By performing ion implantation at an ion implantation amount of about 0 × 10 ¹⁵ atoms / cm ² , a high-concentration impurity layer 11 serving as an N-type drain of the second conductivity type is formed on the semiconductor substrate 9.

Next, a titanium (Ti) film is formed with a thickness of about 100 nm on the entire surface by a sputtering method.

Thereafter, a heat treatment is performed at a temperature of 600 ° C. in a nitrogen atmosphere to cause the titanium film and the silicon of the semiconductor substrate 9 and the titanium film and the polysilicon of the memory gate electrode 1 to react with each other. A silicide film 8 is formed on the surface of the gate electrode 1.

Next, ammonium hydroxide (NH ₄ OH)
The unreacted titanium film is removed by etching using a mixed solution of hydrogen and hydrogen peroxide (H ₂ O ₂ ).

Next, as shown in FIG. 5, an insulating film 12 for a multilayer wiring mainly composed of a silicon dioxide film is formed, a contact window 18 is formed by using a photo-etching technique, and aluminum is formed as a wiring metal 13. Thereby, a nonvolatile memory element is obtained.

In the embodiments described above, the common source 4 is composed of the metal silicide film 2 and the polycrystalline silicon film 3. However, as the common source 4, a metal film, a metal silicide film, and a polycrystalline silicon film 3 are used. It can also be composed of only a silicon film.

The high-concentration impurity layer 11 serving as a drain
And a silicide film 8 of titanium film on the surface of the memory gate electrode 1
Has been described, but a non-volatile memory element having the same effect as the present invention can be obtained only with the high-concentration impurity layer 11 and the memory gate electrode 1 without forming the silicide film 8.

[0038]

According to the present invention, the common source is constituted by a laminated film of a polycrystalline silicon film and a metal silicide film or a low-resistance polycrystalline silicon film, and the common source is made to have a low resistance. Compared to a common source with a diffusion layer,
Miniaturization is possible. Furthermore, since the common source is self-aligned and the memory gate electrodes are formed on both sides of the common source, miniaturization is possible compared to the conventional formation of a memory gate electrode using photolithography. In addition, by making the write voltage sufficiently high with respect to the information read voltage, the MOS gate electrode which has been required conventionally becomes unnecessary,
High integration is easy. As a result, a nonvolatile memory element which has a simple forming process and achieves high integration can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor nonvolatile memory element according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a method for manufacturing a semiconductor nonvolatile memory element according to an embodiment of the present invention.

FIG. 3 is a sectional view illustrating a method for manufacturing a semiconductor nonvolatile memory element according to an embodiment of the present invention.

FIG. 4 is a sectional view illustrating a method for manufacturing a semiconductor nonvolatile memory element according to an embodiment of the present invention.

FIG. 5 is a sectional view illustrating a method for manufacturing a semiconductor nonvolatile memory element according to an embodiment of the present invention.

FIG. 6 is a cross-sectional view illustrating a method for manufacturing a semiconductor nonvolatile memory element in a conventional example.

FIG. 7 is a cross-sectional view illustrating a method for manufacturing a semiconductor nonvolatile memory element in a conventional example.

FIG. 8 is a cross-sectional view illustrating a method for manufacturing a semiconductor nonvolatile memory element in a conventional example.

FIG. 9 is a cross-sectional view illustrating a method for manufacturing a semiconductor nonvolatile memory element in a conventional example.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 memory gate electrode 2 metal silicide film 3 polycrystalline silicon film 4 common source 5 memory oxide film 6 nitride film 7 top oxide film 10 field oxide film 11 high concentration impurity layer 12 diffusion layer 17 polysilicon film

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (2)

(57) [Claims] 1. A field oxide film is formed in a field region around an element region of a semiconductor substrate of a first conductivity type, a polycrystalline silicon film and a metal silicide film are formed over the entire surface, and a common source is formed by photoetching technology. Forming,
Forming a three-layer insulating film consisting of a memory oxide film, a nitride film and a top oxide film, forming a polysilicon film on the entire surface, and etching the polysilicon film by anisotropic dry etching technology, Forming a memory gate electrode on both side walls of the common source; forming a high-concentration impurity layer in the element region in a region aligned with the memory gate electrode; forming a refractory metal film on the entire surface; Performing a reaction between silicon of the high concentration impurity layer and the high melting point metal film, and further reacting the polysilicon film of the memory gate electrode with the high melting point metal film to form a silicide film; Removing the high melting point metal film, forming a multi-layer wiring insulating film mainly composed of a silicon dioxide film, and removing the multi-layer wiring insulating film by photo-etching technology. The method of manufacturing a semiconductor nonvolatile memory device characterized by comprising a step of forming a contact window to the membrane, and forming a wiring metal. 2. A field oxide film is formed in a field region around an element region of a semiconductor substrate of a first conductivity type, a polycrystalline silicon film and a metal silicide film are formed on the entire surface, and a common source is formed by a photo-etching technique. Forming,
Forming a three-layer insulating film including a memory oxide film, a nitride film, and a top oxide film, forming a polysilicon film on the entire surface, and etching the polysilicon film by anisotropic dry etching technology; Forming a memory gate electrode on both side walls of a common source; forming a high concentration impurity layer in the element region in a region aligned with the memory gate electrode; insulating a multi-layer wiring mainly including a silicon dioxide film; A method for manufacturing a semiconductor nonvolatile memory element, comprising: a step of forming a film; a step of forming a contact window in the insulating film for multilayer wiring by a photoetching technique; and a step of forming a wiring metal.