JPH04348080A - Nonvolatile memory - Google Patents

Abstract

PURPOSE:To reduce the area of a cell and to make a decoding method easy by a method wherein a resistor region is formed between the part of a semiconductor substrate under an insulating film and other regions to which a write- inhibit voltage is not applied. CONSTITUTION:A resistor region 11 composed of an N-layer by a diffusion operation is formed between a channel part CH in a semiconductor substraet 1 under an insulating film 4 and a source region 3. The resistor region 11 is formed by using, e.g. phosphorus or arsenic as impurities in the case of the N-layer. When a write-inhibit voltage Vi is applied to a drain electrode D for a memory, a potential distribution from a drain region 2 to the source region 3 does not exist in a part where the voltage is dropped to O V under the insulating film 4. As a result, an electric charge is not trapped inside the insulating film 4, strictly speaking, inside a nitride film 7, and an aim not to write the electric charge can be achieved. Consequently, it is not required to from a transistor for write-inhibit, the area of a memory cell can be reduced, and the number of interconnections required in a write operation can be reduced.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to trap type nonvolatile memories such as MNOS and MONOS.

0002

2. Description of the Related Art A semiconductor device has been proposed in which a plurality of trap-type nonvolatile memories (hereinafter referred to as "memories") of this type are connected in a matrix so that writing and erasing can be freely performed in a desired matrix portion. There is. In such a device, there is a memory to which data can be written and a memory to which data cannot be written, but in order to prevent data from being written to memory that does not require writing, for example, as shown in FIG. Transistors TR1 and TR2 are connected to each memory M1 and M2 respectively.
It is common practice to provide them in pairs.

That is, in FIG. 4, when a program voltage VPP is applied to the gate to write to the memory M1, a write inhibit voltage Vi is applied to the drain of the memory M2 which does not require writing. At this time, if the transistor TR2 does not exist, a voltage Vi is applied to the drain region 2 of this memory M2 shown in FIG. At a portion W close to 3, it becomes 0V. Therefore, a charge writing bias is applied between the surface of the semiconductor substrate 1 corresponding to this portion W and the gate electrode 5, and the insulating film 4 corresponding to that portion W is applied.
Electric charge will be accumulated in the area, and writing will be performed.

However, as shown in FIG. 4, since the transistor TR2 is present and the transistor TR2 is open (OFF state), the voltage of the portion W does not become 0V, and therefore unnecessary writing occurs. is prevented. In addition, in FIG. 5, 6 is an oxide film of SiO2, and 7 is an S
It is an iN nitride film.

A device in which a memory and a transistor are provided in pairs as shown in FIG. 4 is also disclosed in Japanese Patent Application Laid-Open No. 59-211281. Also, Hitachi Review VOL68, N
O. 7 (1986-7) proposed a memory in which two gates were added in addition to the memory portion 8 on one substrate as shown in FIG. While the memory shown in FIG. 4 has two transistors per cell, the memory shown in FIG. 6 has three transistors per cell.

[0006]

However, the conventional example described above has a drawback in that the area of the cell becomes large because a transistor part is formed in addition to the memory part. Moreover, in the conventional example shown in FIG. 4, there is a source line for each column of the matrix, which makes the cells unavoidably large and the decoding method unavoidable. Furthermore, the conventional example shown in FIG. 6 also has the disadvantage that the area is large, and the decoding method is complicated, making it inconvenient to use. The present invention has been made in view of these points, and it is an object of the present invention to provide a nonvolatile memory whose cell area is relatively small and whose decoding method is easy.

[0007]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides an insulator capable of trapping charges between the semiconductor substrate and the gate electrode on the channel between the source region and the drain region of the semiconductor substrate. In a nonvolatile memory in which a film is interposed and a write inhibit voltage is applied to one of the source region and the drain region, there is a gap between a semiconductor substrate portion under the insulating film and another region to which the write inhibit voltage is not applied. A resistor region is provided in between.

[0008]

[Function] According to such a configuration, for example, when the source is grounded and a write inhibit voltage is applied to the drain, the voltage drop is suppressed by the resistor region, and the substrate potential (for example, 0 V) is maintained even on the source region side. ). Therefore, even if there is no transistor dedicated to write blocking as in the prior art, charges will not be trapped (written) in the insulating film.

[0009]

EXAMPLES The present invention will be explained below according to examples shown in the figures. In FIG. 1(a) in which the present invention is implemented, 11 is a resistor made of a diffusion N layer provided between a portion of the semiconductor substrate 1 under the insulating film 4 (therefore, the channel CH) and the source region 3. This is the body area. In the case of an N-layer, this resistor region 11 is formed using, for example, phosphorus or arsenic as an impurity. Incidentally, the source region 3 is provided at a position shifted to the left in the figure by an amount corresponding to the formation of the resistor region 11.

When a write prohibition voltage Vi is applied to the drain electrode D of the memory constructed in this way, the potential distribution from the drain region 2 to the source region 3 is as shown in (b) in FIG.
), and there is no part where the voltage drops to 0V under the insulating film 4. Therefore, charges are not trapped in the insulating film 4 (strictly speaking, the nitride film 7), and the purpose of not writing charges can be achieved.

FIG. 2 shows an equivalent circuit of FIG. 1(a), in which R represents the resistance due to the resistor region 11.

In FIG. 1, the memory section (therefore the insulating film 4
) The potential V at the left end of the semiconductor substrate part under ) is channel C.
It is determined by the ratio of H to the resistance of the resistor region 11. If the write voltage applied to the gate electrode 5 is VPP, the potential difference with the channel portion at the left end is VP.
PV, so the values of Vi and the resistance R of the resistor region 11 are selected so that this value is below the write critical voltage.

In the above embodiment, the write inhibit voltage V
i is applied to the drain region 2 side, and the resistor region 11 is provided on the source region 3 side, but the source region 3 and drain region 2 are reversed and the write voltage Vi is applied to the source region. However, similar effects can be obtained even if the resistor region 11 is provided on the drain region side.

Next, FIG. 3 shows a memory matrix circuit using the memory having the configuration shown in FIG. 1. In this circuit, 12 is an X decoder and 13 is a Y decoder. If writing is to be performed only in the memories within the dotted line frame 14, the substrates 1 and source electrodes S of all memories are grounded, and the word lines L1, L2, L4, L5 and bit line L7 are grounded, and the word lines L1, L2, L4, L5 and bit line L7 are - The write voltage VPP may be applied to the bit line L3, and the write inhibit voltage Vi may be applied to the bit lines L6 and L8. In this way, when the memory of this embodiment is used, the number of wires in the memory matrix circuit is reduced.

[0015]

[Effects of the Invention] As explained above, according to the present invention, compared to conventional non-volatile memory, there is no need to provide a write-inhibiting transistor, so the area of the memory cell can be reduced, and the area required for writing can be reduced. This has the effect that the number of wiring lines can be reduced, and is extremely effective.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a nonvolatile memory embodying the present invention.

[Figure 2] Its equivalent circuit diagram.

FIG. 3 is a circuit diagram showing a memory matrix circuit using the memory of FIG. 1;

FIG. 4 is a diagram showing a part of a conventional memory matrix circuit.

FIG. 5 is a diagram showing the configuration of a conventional nonvolatile memory.

FIG. 6 is an equivalent circuit diagram of another conventional example.

[Explanation of symbols]

1 Semiconductor device 2 Drain region 3 Source area 4 Insulating film 5 Gate electrode 6 Oxide film 7 Nitride film 11 Resistor area

Claims (1)

[Claims] 1. An insulating film capable of trapping charges is interposed between the semiconductor substrate and the gate electrode on the channel between the source region and the drain region of the semiconductor substrate, and the source
In a nonvolatile memory in which a write inhibit voltage is applied to one of a write inhibit voltage and a write inhibit voltage, a resistor region is provided between a semiconductor substrate portion under the insulating film and another region to which the write inhibit voltage is not applied. Non-volatile memory characterized by