JPH02117156A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02117156A JPH02117156A JP27132788A JP27132788A JPH02117156A JP H02117156 A JPH02117156 A JP H02117156A JP 27132788 A JP27132788 A JP 27132788A JP 27132788 A JP27132788 A JP 27132788A JP H02117156 A JPH02117156 A JP H02117156A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- insulating substrate
- cracks
- parallel
- conductors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 23
- 239000004020 conductor Substances 0.000 claims abstract description 68
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 abstract description 9
- 230000008642 heat stress Effects 0.000 abstract 2
- 238000005476 soldering Methods 0.000 abstract 2
- 229910000831 Steel Inorganic materials 0.000 description 8
- 239000010959 steel Substances 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 230000008646 thermal stress Effects 0.000 description 6
- 238000009413 insulation Methods 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000005452 bending Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Combinations Of Printed Boards (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は絶縁基板上にパワートランジスタ等を有する
半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having a power transistor or the like on an insulating substrate.
第２図は従来の絶縁基板を有する半導体装置の一例を示
す断面図、第３図はその絶縁基板の断面図及び平面図で
ある。これらの図において、（１）は半導体素子を支持
するセラミック等の絶縁基板、（２）は表面導体パター
ンで、上記絶縁基板（１）の一方の面に接合された鋼材
などの半田付は可能な金属材で構成されると共に、半導
体装置の回路の一部を形成するものであり、半導体素子
などを支持する支持部（２ａ） （２ｄ）、この支持部
（２ａ）と連って一体に構成され、支持部（２ａ）に電
流を供給する給電部（２ｂ）、及び後述のリード線の中
継端子等である端子部（２ｃ） （２ｅ）とからなって
いる、（３ａ） （３ｂ）はパワートランジスタ等の半
導体素子で、それぞれ半田（４ａ） （４ｂ）によって
上記支持部（２ａ） （２ｄ）に固着されている。（（
５）は半導体装置の外部の回路と接続される外部電極で
、半田（４ｃ）によって上記端子部（２ｅ）に固着され
ている。（６ａ＞ （６ｂ）はアルミニウム線などのリ
ード線で、半導体素子（３ａ） （３ｂ）上の電極と上
記端子部（２ｃ） （２ｅ）とを接続している。（７１
は裏面導体パターンで、上記絶縁基板（１）の他方の面
に接合され、鋼材などの金属材で構成されている。（８
）は鋼材などの放熱板で、半田（４ｄ）により上記裏面
導体パターン（７）に固着されている。FIG. 2 is a sectional view showing an example of a conventional semiconductor device having an insulating substrate, and FIG. 3 is a sectional view and a plan view of the insulating substrate. In these figures, (1) is an insulating substrate made of ceramic or the like that supports the semiconductor element, and (2) is a surface conductor pattern. It is possible to solder the steel material etc. bonded to one side of the insulating substrate (1). It is made of a metal material that forms part of the circuit of a semiconductor device, and is integrated with the support part (2a) (2d) that supports the semiconductor element, etc. (3a) (3b), consisting of a power supply part (2b) that supplies current to the support part (2a), and terminal parts (2c) (2e) which are relay terminals for lead wires described later. are semiconductor elements such as power transistors, which are fixed to the supporting parts (2a) and (2d) with solders (4a) and (4b), respectively. ((
5) is an external electrode connected to a circuit outside the semiconductor device, and is fixed to the terminal portion (2e) with solder (4c). (6a> (6b) is a lead wire such as an aluminum wire, which connects the electrodes on the semiconductor elements (3a) (3b) and the terminal parts (2c) (2e). (71
is a back conductor pattern, which is joined to the other surface of the insulating substrate (1) and is made of a metal material such as steel. (8
) is a heat dissipation plate made of steel or the like, which is fixed to the back conductor pattern (7) with solder (4d).
以上の様に構成された半導体装置において、半導体素子
（３ａ）に大きな電流を供給する場合、上記給電部（２
ｂ）を経て流すことになるが、この給電部（２ｂ）の電
流容量はその断面積に依存するため、その幅を大きくす
るか厚さｔ４を厚くする必要がある。しかし、給電部（
２ｂ）の幅を広くすると、表面導体パターン（２）が大
きくなり、半導体装置が大きくなるという問題点がある
ため、厚さｔ４を厚くするのが得策である。In the semiconductor device configured as described above, when supplying a large current to the semiconductor element (3a), the power supply section (2
b), but since the current capacity of this power supply section (2b) depends on its cross-sectional area, it is necessary to increase its width or thickness t4. However, the power supply (
If the width of 2b) is increased, the surface conductor pattern (2) becomes larger and the semiconductor device becomes larger. Therefore, it is advisable to increase the thickness t4.
ところで、従来のセラミックの絶縁基板（１）の表裏面
に鋼材をパターニングする方法としては、直接接合法及
び絶縁基板（１）と鋼材との間に例えばＴｉ−Ｃｕ−Ａ
ｇから成る金属層を介在させて接合する活性金属法と呼
ばれる接合法がある。しかし、直接接合法の場合は１０
７０℃前後、活性金属法の場合でも８５０℃前後の高温
での接合を余儀なくされ、また、セラミックの絶縁基板
（１）と鋼材の熱膨張係数が大きく異なることにより、
接合完了時点でバターニングされている鋼材の境界近辺
に大きな熱応力が残留することになる。By the way, conventional methods for patterning steel materials on the front and back surfaces of a ceramic insulating substrate (1) include a direct bonding method and a method using, for example, a Ti-Cu-A bonding method between the insulating substrate (1) and the steel material.
There is a bonding method called the active metal method in which bonding is performed by interposing a metal layer consisting of g. However, in the case of direct bonding method, 10
Bonding is forced at high temperatures of around 70°C, or around 850°C even in the case of the active metal method, and the thermal expansion coefficients of the ceramic insulating substrate (1) and the steel material are significantly different.
At the time of completion of joining, large thermal stress remains near the boundary of the patterned steel materials.
上記熱応力の残留した絶縁基板（１）（例えば厚さ０、
６〜０．７ｍｍ ）を例えば−４０℃〜１２５℃のヒー
トサイクル試験にかけると、比較的少ないサイクル数で
第３図（３Ａ） 、 （３Ｂ）に示す様に導体パターン
の周辺に沿う部分での微小クラック（９）又は導体パタ
ーンのコーナ一部分での微小クラック（１０１が発生し
、絶縁基板（１）の絶縁性が保持できないという問題が
あった。また、このクラック（９１ＱＯＩの発生はバタ
ーニングされている鋼材の厚さｔ４と密接な関係があり
、厚さが大きい程クラックが発生するまでのサイクル数
が少なくなるということが確認されており、上記例示の
厚さ程度の絶縁基板（１）に対しては実用上クラックの
発生が抑制されるｔ ａ ” ０．３ｍｍ程度以下でし
か使えず、従って、パターニングされている回路を流れ
る電流値が制限されるという不都合があり、比較的小さ
な電流容量の半導体装置にしか使えないという問題点が
あった。Insulating substrate (1) with residual thermal stress (for example, thickness 0,
6 to 0.7 mm) is subjected to a heat cycle test at, for example, -40°C to 125°C, the area along the periphery of the conductor pattern will change after a relatively small number of cycles as shown in Figures 3 (3A) and (3B). There was a problem that the insulating properties of the insulating substrate (1) could not be maintained due to the occurrence of micro-cracks (9) or micro-cracks (101) at some corners of the conductor pattern. It has been confirmed that there is a close relationship with the thickness t4 of the steel material, and the larger the thickness, the fewer the number of cycles until cracks occur. ), it can be used only with a t a of about 0.3 mm or less, which suppresses the occurrence of cracks, and therefore has the disadvantage that the current value flowing through the patterned circuit is limited. The problem was that it could only be used for current capacity semiconductor devices.
この発明は上記のような問題点を解決するためになされ
たもので、絶縁基板と表面導体パターンとの間の残留熱
応力を低減し、絶縁基板にクラックが生じるのを抑制す
ることにより絶縁基板の絶縁性を保持し、且つ、表面導
体パターンに大きな電流を流せるようにした半導体装置
を提供することを目的とする。This invention was made to solve the above-mentioned problems, and it reduces the residual thermal stress between the insulating substrate and the surface conductor pattern, and suppresses the occurrence of cracks in the insulating substrate. An object of the present invention is to provide a semiconductor device which maintains insulation properties and allows a large current to flow through a surface conductor pattern.
この発明に係る半導体装置は、絶縁基板に設けられた導
体を互いに順隔した複数導体で構成すると共に、各導体
を電気的に並列接続したものである。The semiconductor device according to the present invention includes a plurality of conductors provided on an insulating substrate that are spaced apart from each other, and each conductor is electrically connected in parallel.
この発明においては、絶縁基板に設けられた導体を互い
に離隔した例えば第１の導体と第２の導体からなる複数
導体で構成し、絶縁基板に接合された第１の導体を薄く
することにより第１の導体が接接絶縁基板の撓みに追随
するようにして残留熱応力を低減し、また、第２の導体
と第１の導体との間を離隔させることにより絶縁基板及
び第１の導体が撓んで湾曲しても、この撓みが上記離隔
された間隙内に収まり、第２の導体には接触しないよう
にして絶縁基板にクラックが発生するのを抑制している
。また、第１の導体と第２の導体を電気的に並列接続し
、電流を分流するようにしているため、第２の導体の断
面積を大にすることにより、大電流の通電が可能となる
。In this invention, the conductor provided on the insulating substrate is composed of a plurality of conductors separated from each other, for example, a first conductor and a second conductor, and the first conductor bonded to the insulating substrate is thinned. The first conductor follows the deflection of the insulated substrate to reduce residual thermal stress, and the second conductor and the first conductor are separated from each other so that the insulated substrate and the first conductor Even if it bends and curves, this bending is contained within the spaced gap and does not come into contact with the second conductor, thereby suppressing the occurrence of cracks in the insulating substrate. Furthermore, since the first conductor and the second conductor are electrically connected in parallel and the current is divided, it is possible to carry a large current by increasing the cross-sectional area of the second conductor. Become.
以下、この発明の一実施例を図について説明する。第１
図は、この発明による半導体装置の絶縁基板の断面図及
び平面図である。この図において、（１）は絶縁基板、
（力は裏面導体パターン、（１１）は従来の表面導体パ
ターン（２）と同様の第１の導体であるが、その厚さｔ
ｌは薄く、絶縁基板（１）の撓みに追随するものである
。これら裏面導体パターン（７）と第１の導体（１１）
は、クラックの発生が抑制される例えば０．３ｍｍ以下
の厚さとされ、直接接合法により絶縁基板（１）に接合
されている。（１２）は第１の導体（１１）のうち給電
部（ｌｌｂ）に対して間隔ｔｚ（例えば０．１ｍ５）を
保って並行配置された厚さｔ、の第２の導体である。こ
れらの第１の導体（１１）の給電部（ｌｌｂ＞と第２の
導体（１２）とは互に離隔した複数導体として構成され
、第２の導体（１２）の端の部分で半田（１３ａ） （
１３ｂ）により上記給電部（ｌｌｂ）と固着され電気的
に並列接続されている。半田（１３ａ）（１３ｂ）は又
、給電部（Ｉｌｂ＞と第２の導体（１２）とを間隔ｔ２
を保って離隔させるスペーサとしての機能もはなすもの
である。An embodiment of the present invention will be described below with reference to the drawings. 1st
The figures are a sectional view and a plan view of an insulating substrate of a semiconductor device according to the present invention. In this figure, (1) is an insulating substrate;
(The force is the back conductor pattern, (11) is the first conductor similar to the conventional front conductor pattern (2), but its thickness is t
l is thin and follows the deflection of the insulating substrate (1). These back conductor patterns (7) and the first conductor (11)
has a thickness of, for example, 0.3 mm or less to suppress the occurrence of cracks, and is bonded to the insulating substrate (1) by a direct bonding method. (12) is a second conductor of the first conductor (11) having a thickness t and arranged in parallel with the power feeding part (llb) with an interval tz (for example, 0.1 m5) maintained therebetween. The power feeding part (llb> of the first conductor (11) and the second conductor (12) are configured as multiple conductors spaced apart from each other, and solder (13a) is applied at the end of the second conductor (12). ) (
13b), it is fixedly connected to the power feeding section (llb) and electrically connected in parallel. The solder (13a) (13b) also connects the power supply part (Ilb> and the second conductor (12) with a distance t2
It also functions as a spacer to maintain and separate the two.
上記のように構成された半導体装置においては、第１の
導体（１１）の厚さｔｌは薄く、絶縁基板（１）の撓み
に追随するようにしであるので、第１の導体（１１）と
絶縁基板（１）との間で生じる残留熱応力を低減し得る
。また、上記第１の導体（１１１の給電部（ｌｌｂ）と
第２の導体（１２）とは互に離隔して並行配置され、並
列接続されているので、第２図に示す放熱板８と絶縁基
板（１）との間で、残留熱応力により絶縁基板（１）及
び第１の導体（１１）が撓んで湾曲しても、その撓みが
第１の導体（Ｉ ｌ）と第２の導体（１２）との間（１
３ｃ）の間隔ｔ２内に数次り、第２の導体（１２）には
接触しないようにして、絶縁基板（１）にクラックが発
生するのを抑制し得る。In the semiconductor device configured as described above, the thickness tl of the first conductor (11) is thin and is designed to follow the deflection of the insulating substrate (1). Residual thermal stress generated between the insulation substrate (1) and the insulation substrate (1) can be reduced. Furthermore, since the power feeding part (llb) of the first conductor (111) and the second conductor (12) are arranged parallel to each other and spaced apart from each other and are connected in parallel, the heat sink 8 shown in FIG. Even if the insulating substrate (1) and the first conductor (11) are bent and curved due to residual thermal stress between the insulating substrate (1) and the insulating substrate (1), the bending will cause the first conductor (I l) Between the conductor (12) (1
By avoiding contact with the second conductor (12) several times within the interval t2 of 3c), it is possible to suppress the occurrence of cracks in the insulating substrate (1).
さらにまた、第１の導体（ＩＩ）の給電部（Ｉｌｂ）と
第２の導体（１２）との断面積の総和によって通電容量
が決定されるため、第１の導体（Ｉｌｌの厚さｔｌに限
度があっても第２の導体の厚さｔ、を適宜選ぶことによ
り通電電流値に必要な断面積を得ることができる。Furthermore, since the current carrying capacity is determined by the sum of the cross-sectional areas of the power feeding part (Ilb) of the first conductor (II) and the second conductor (12), the thickness tl of the first conductor (Ill) Even if there is a limit, the cross-sectional area necessary for the current value can be obtained by appropriately selecting the thickness t of the second conductor.
なお、上記実施例では第２の導体（１２）を絶縁基板（
１）の表面に設けた例を示したが、絶縁基板（１）の側
面に設け、第１の導体＜１１）の給電部＜１ｌｂ）と電
気的に並列接続するようにしても同様の効果が得られる
。In addition, in the above embodiment, the second conductor (12) is connected to an insulating substrate (
1), but the same effect can be obtained by providing it on the side surface of the insulating substrate (1) and electrically connecting it in parallel with the power supply part <1lb) of the first conductor <11). is obtained.
以上のように、この発明は、絶縁基板上に設けられる導
体を離隔した複数導体で構成すると共に、各導体を電気
的に並列接続するようにしたため、絶縁基板にクラック
が発生するのが抑制され、絶縁性にすぐれ、且つ、大き
な電流容量を持つ半導体装置を得ることができる。As described above, in this invention, the conductor provided on the insulating substrate is composed of a plurality of conductors separated from each other, and each conductor is electrically connected in parallel, so that the occurrence of cracks in the insulating substrate is suppressed. , a semiconductor device having excellent insulation properties and a large current capacity can be obtained.
第１図はこの発明の一実施例を示す断面図及び平面図、
第２図、第３図は従来の半導体装置の構成を示す断面図
及び平面図である。
図において、（１）は絶縁基板、（２１，（７）はそれ
ぞれ表面及び裏面導体パターン、（３ａ） （３ｂ）は
半導体素子、（４ａ） 〜（４ｄ）、 （１３ａ）、
（１３ｂ）は半田、Ｖ５）は外部電極、（６ａ） （６
ｂ）はリード線、（５）は放熱板、（９）、αＯ）はク
ラック、（１１）は第１の導体、（１２）は第２の導体
である。
なお、各図中同一符号は同一または相当部分を示す。
第１図
代理人 弁理士 大 岩 増 雄FIG. 1 is a sectional view and a plan view showing an embodiment of the present invention,
FIGS. 2 and 3 are a cross-sectional view and a plan view showing the structure of a conventional semiconductor device. In the figure, (1) is an insulating substrate, (21 and (7) are front and back conductor patterns, respectively, (3a) and (3b) are semiconductor elements, (4a) to (4d), (13a),
(13b) is solder, V5) is external electrode, (6a) (6
b) is a lead wire, (5) is a heat sink, (9), αO) is a crack, (11) is a first conductor, and (12) is a second conductor. Note that the same reference numerals in each figure indicate the same or corresponding parts. Figure 1 Agent Masuo Oiwa, patent attorney
Claims (1)
けられ上記半導体素子に接続された導体を備え、この導
体を互いに離隔した複数導体で構成すると共に、各導体
を電気的に並列接続したことを特徴とする半導体装置。An insulating substrate supporting a semiconductor element, and a conductor provided on the insulating substrate and connected to the semiconductor element, the conductor being composed of a plurality of conductors spaced apart from each other, and each conductor being electrically connected in parallel. Characteristic semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27132788A JPH02117156A (en) | 1988-10-26 | 1988-10-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27132788A JPH02117156A (en) | 1988-10-26 | 1988-10-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02117156A true JPH02117156A (en) | 1990-05-01 |
Family
ID=17498506
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27132788A Pending JPH02117156A (en) | 1988-10-26 | 1988-10-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02117156A (en) |
-
1988
- 1988-10-26 JP JP27132788A patent/JPH02117156A/en active Pending
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