JPH0444252A - Wiring board - Google Patents
Wiring boardInfo
- Publication number
- JPH0444252A JPH0444252A JP2149096A JP14909690A JPH0444252A JP H0444252 A JPH0444252 A JP H0444252A JP 2149096 A JP2149096 A JP 2149096A JP 14909690 A JP14909690 A JP 14909690A JP H0444252 A JPH0444252 A JP H0444252A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- substrate
- pattern
- approximately
- protruding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000004020 conductor Substances 0.000 claims abstract description 7
- 239000004065 semiconductor Substances 0.000 abstract description 10
- 239000000919 ceramic Substances 0.000 abstract description 8
- 238000000034 method Methods 0.000 abstract description 6
- 238000010304 firing Methods 0.000 abstract description 2
- 239000000463 material Substances 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 2
- 229910000831 Steel Inorganic materials 0.000 abstract 1
- 238000004080 punching Methods 0.000 abstract 1
- 239000010959 steel Substances 0.000 abstract 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
Landscapes
- Structure Of Printed Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ハイブリッドＩＣあるいは電力用半導体モジ
ュールなどに用いられる配線基板に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a wiring board used in a hybrid IC or a power semiconductor module.
ハイブリッドＩＣあるいは電力用半導体モジニールなど
において半導体素子などの部品の実装に用いられる配線
基板としては、酸化アルミニウム（ＭｚＯｓ）あるいは
窒化アルミニウム （Ａｌ）などのセラミック基板の両
面に全面に０．３閣程度の厚さの銅板を貼付け、一面上
のｗＩ板からエツチング等でパターンを形成して配線と
するものが知られている。この基板上に部品を実装し、
部品の端子と配線とを直接接着するか、あるいは導線を
用いて接続する。このような銅貼り基板は、熱伝導が良
く、実装部品のレイアウトあるいは積層構造の簡略化が
可能である利点を持っている。As a wiring board used for mounting components such as semiconductor elements in hybrid ICs or power semiconductor modules, ceramic substrates such as aluminum oxide (MzOs) or aluminum nitride (Al) are coated on both sides with a thickness of about 0.3 mm on the entire surface. It is known that wiring is formed by pasting a thick copper plate and forming a pattern by etching or the like from the wI plate on one side. Mount components on this board,
Terminals of components and wiring are directly bonded or connected using conductive wires. Such a copper-clad board has the advantage of good thermal conductivity and the ability to simplify the layout of mounted components or the laminated structure.
上述のような配＆ｌ基板においては、銅線パターン相互
間に間隙により絶縁されている。しかし、組立工程で一
方の配線上に接着された部品の上面の端子と他方の配線
を、アルミニウムあるいは金の導線のボンディング等に
よって接続する場合、導線がたれて配線に接触すると短
絡等が起きる問題がある。第２図はそのような状態を示
し、セラミック基板１の裏面には一面に銅板２が、表面
には銅板からなる配線パターン３１，３２．３３が被着
しており、配線パターン３１の上に固着された半導体チ
ップ４の上面の電極と配線パターン３２．３３がＡ７線
５によって接続されているが、ループ状にした配線５が
たれて配１１３１に接触し、短絡が生している。In the wiring board as described above, the copper wire patterns are insulated from each other by gaps. However, when connecting a terminal on the top surface of a component glued onto one wiring during the assembly process by bonding aluminum or gold conductive wire, there is a problem that short circuits may occur if the conductive wire sags and comes into contact with the wiring. There is. FIG. 2 shows such a state, with a copper plate 2 covering one side of the back surface of the ceramic substrate 1, and wiring patterns 31, 32, and 33 made of copper plates covering the front surface. The electrodes on the upper surface of the fixed semiconductor chip 4 and the wiring patterns 32, 33 are connected by the A7 wire 5, but the looped wiring 5 sags and contacts the wiring 1131, causing a short circuit.
このような障害を防止するために、ワイヤボンダにプル
テスト機構を備えてワイヤループを持上げる方法あるい
はボンディングの際に人手によってワイヤループを持上
げる方法がある。しかし、ボンダの稼働率の低下あるい
は工数の増加を招き、組立工程の合理化のネックとなっ
ている。In order to prevent such troubles, there is a method in which the wire bonder is equipped with a pull test mechanism to lift the wire loop, or a method in which the wire loop is manually lifted during bonding. However, this reduces the bonder's operating rate or increases the number of man-hours, which is a bottleneck in streamlining the assembly process.
本発明の目的は、配線への接続のための導線が他の配線
に接触することのない配線基板を提供することにある。An object of the present invention is to provide a wiring board in which conductive wires for connection to wiring do not come into contact with other wiring.
上記の目的を達成するために、本発明は、絶縁性基板の
一面に板状の導電体よりなる配線のパターンを有する配
線基板において、絶縁性基板の前記一面に突出部とその
突出部にはさまれ配線の厚さ以上低い平地部とが形成さ
れ、配線がその平地部上に被着しているものとする。In order to achieve the above object, the present invention provides a wiring board having a wiring pattern made of a plate-like conductor on one surface of an insulating substrate, a protrusion on the one surface of the insulating substrate, and a protrusion on the one surface of the insulating substrate. It is assumed that a flat area with a thickness equal to or greater than the thickness of the sandwiched wiring is formed, and the wiring is adhered to the flat area.
〔作用〕
配線と配線の間には配線の厚さより高い突出部が存在す
るため、一つの配線パターン上に固着される部品の上面
の端子と他の配線パターンとを接読する導線の中間部は
その突出部で持上げられ、配線パターンに接触すること
がない。[Operation] Since there is a protruding part between the wirings that is higher than the thickness of the wiring, the intermediate part of the conductor that reads the terminal on the top surface of the component fixed on one wiring pattern and the other wiring pattern. is lifted by its protrusion and does not come into contact with the wiring pattern.
第１図に本発明の一実施例の配線基板を用いた半導体装
置を示す０図より明らかなようにＡＺ 、０゜あるいは
Ａ７Ｎからなるセラミック基板１の上面には高さ約０．
５■の線状の突出部６が形成されていル、突出部６の幅
は１日程度である。突出部６の間には低い平地部７が存
在する。このようなセラミック基板１は、素材のグリー
ンシートをプレスを用いて切断する工程の際に同時に一
面に凹凸をつけ、そのあと約１４００℃の高温で焼成す
ることによって作成される０次いで、予め打抜きによっ
てパターンに形成した厚さ０．３日の銅板を基板１の平
地部７に密着させ、１０００℃前後で基板に焼付けるこ
とによって配線パターン３１．３２．３３を形成する。As is clear from FIG. 1, which shows a semiconductor device using a wiring board according to an embodiment of the present invention, the upper surface of a ceramic substrate 1 made of AZ, 0°, or A7N has a height of approximately 0.0°.
A linear protrusion 6 of 5 mm is formed, and the width of the protrusion 6 is about 1 day. A low flat area 7 exists between the protrusions 6. Such a ceramic substrate 1 is created by making a green sheet of material uneven on one side during the process of cutting it using a press, and then firing it at a high temperature of about 1400°C. A copper plate having a thickness of 0.3 days formed into a pattern is brought into close contact with the flat area 7 of the substrate 1, and is baked onto the substrate at around 1000° C. to form wiring patterns 31, 32, and 33.
このあと、直径２００〜４００μのＡｌｖＡ５のポンデ
ィングによって配線パターン３１の上に固着された半導
体チップ４の上面の電極と配線パターン３２．３３とを
それぞれ接続するカベ突出部６の上面は配線の上面より
０．２鶴高いためＡｊ導線のループがたれ下がっても、
図示のように突出部６の上面に接触し、配線パターン３
２あるいは３３に接触することがなく、短絡の発生が防
止される。After this, by bonding AlvA5 with a diameter of 200 to 400μ, the upper surface of the wall protrusion 6 that connects the electrode on the upper surface of the semiconductor chip 4 fixed on the wiring pattern 31 and the wiring pattern 32, 33, respectively, is the upper surface of the wiring. Even if the loop of the Aj conductor hangs down because it is 0.2 crane higher than the
The wiring pattern 3 contacts the upper surface of the protrusion 6 as shown in the figure.
2 or 33, thereby preventing short circuits from occurring.
突出部６の断面形状は、第１図あるいは第３図（４）に
示すような方形に限定されることはなく、第３図（ｂｌ
に示すような三角形状、あるいは第３図（ｃｌに示すよ
うな長円形状であってもよい、また、突出部６をセラミ
ック基板１と一体に成形しないで、平板状のセラミック
基板に全面に貼付けた銅板からエツチングにより配線パ
ターンを形成したのち、セラミックあるいは樹脂よりな
る条状絶縁体を接着して突出部としてもよい、この場合
は、任意の配線パターンの形成が容易であるという利点
がある。The cross-sectional shape of the protrusion 6 is not limited to the rectangular shape shown in FIG. 1 or FIG.
It may be a triangular shape as shown in FIG. 3 or an elliptical shape as shown in FIG. After forming a wiring pattern by etching the pasted copper plate, a strip insulator made of ceramic or resin may be adhered to form a protrusion.In this case, the advantage is that it is easy to form any wiring pattern. .
接続にＡｕ′ＩＩＡを用いる場合は、線径が２５〜５０
ｆｌであり、配線パターン間の間隔、すなわち突出部の
幅も０．２鶴程度に狭くされる。When using Au'IIA for connection, the wire diameter is 25 to 50.
fl, and the spacing between the wiring patterns, that is, the width of the protrusion, is also narrowed to about 0.2 squares.
本発明によれば、絶縁性基板の一面上の配線パターンの
間に基板の突出部を介在させることにより、配線に接続
される導線の中間部がその突出部に持ち上げられ、望ま
しくない配線への接触が阻止されるので、配線間の短絡
を防止できた。これにより、導線の中間部の持ち上げ作
業が不要となり、組立時間の短縮ができ、また組立作業
のライン化に対応することも可能になった。According to the present invention, by interposing the protruding part of the board between the wiring patterns on one surface of the insulating substrate, the middle part of the conducting wire connected to the wiring is lifted by the protruding part, thereby preventing undesired wiring. Since contact is prevented, short circuits between wires can be prevented. This eliminates the need to lift the middle part of the conductor, shortens assembly time, and allows for assembly lines.
第１図は本発明の一実施例の配線基板を用いた半導体装
置の断面図、第２図は従来の配線基板を用いた半導体装
置の断面図、第３図は本発明に基づく絶縁性基板突出部
の形状例をｔａｌ〜ｔｃ）に示す断面図である。
Ｉ：セラミック基板、３１．３２．３３ ：配線パター
ン、４：半導体ナツプ、５：Ｍ線、６：基板突出部、７
：基板平地部、−、
代理人弁理士 山 口 巖 て
・（アFIG. 1 is a sectional view of a semiconductor device using a wiring board according to an embodiment of the present invention, FIG. 2 is a sectional view of a semiconductor device using a conventional wiring board, and FIG. 3 is an insulating substrate according to the present invention. FIG. 3 is a cross-sectional view showing an example of the shape of a protrusion from tal to tc. I: Ceramic substrate, 31.32.33: Wiring pattern, 4: Semiconductor nap, 5: M line, 6: Substrate protrusion, 7
:Substrate Plains Department, -, Representative Patent Attorney Iwao Yamaguchi (A)
Claims (1)
ターンを有するものにおいて、絶縁性基板の前記一面に
突出部とその突出部にはさまれ配線の厚さ以上低い平地
部とが形成され、配線がその平地部上に被着しているこ
とを特徴とする配線基板。1) In a device that has a wiring pattern made of a plate-shaped conductor on one surface of an insulating substrate, the one surface of the insulating substrate has a protruding part and a flat part sandwiched between the protruding part and lower than the thickness of the wiring. 1. A wiring board characterized in that the wiring board is formed on a flat surface of the wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2149096A JPH0444252A (en) | 1990-06-07 | 1990-06-07 | Wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2149096A JPH0444252A (en) | 1990-06-07 | 1990-06-07 | Wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0444252A true JPH0444252A (en) | 1992-02-14 |
Family
ID=15467610
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2149096A Pending JPH0444252A (en) | 1990-06-07 | 1990-06-07 | Wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0444252A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015015275A (en) * | 2013-07-03 | 2015-01-22 | 三菱電機株式会社 | Ceramic circuit board, ceramic circuit board with heat sink, and manufacturing method of ceramic circuit board |
| WO2017174356A1 (en) * | 2016-04-04 | 2017-10-12 | Vishay Semiconductor Gmbh | Electronic unit |
-
1990
- 1990-06-07 JP JP2149096A patent/JPH0444252A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015015275A (en) * | 2013-07-03 | 2015-01-22 | 三菱電機株式会社 | Ceramic circuit board, ceramic circuit board with heat sink, and manufacturing method of ceramic circuit board |
| WO2017174356A1 (en) * | 2016-04-04 | 2017-10-12 | Vishay Semiconductor Gmbh | Electronic unit |
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