JPH02113329U - - Google Patents

Info

Publication number
JPH02113329U
JPH02113329U JP2190089U JP2190089U JPH02113329U JP H02113329 U JPH02113329 U JP H02113329U JP 2190089 U JP2190089 U JP 2190089U JP 2190089 U JP2190089 U JP 2190089U JP H02113329 U JPH02113329 U JP H02113329U
Authority
JP
Japan
Prior art keywords
semiconductor wafer
pedestal
shaped depression
semiconductor
diameter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2190089U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP2190089U priority Critical patent/JPH02113329U/ja
Publication of JPH02113329U publication Critical patent/JPH02113329U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Packaging Frangible Articles (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の装置の一実施例を示す構造図
、第2図は従来の装置の構造図である。 1……窪み、11……内周部、12……底面部
、13……縁部、2……突起、21……隙間、3
……着脱溝、4……半導体ウエーハ、41……オ
リエンテーシヨンフラツト。
FIG. 1 is a structural diagram showing an embodiment of the device of the present invention, and FIG. 2 is a structural diagram of a conventional device. 1... Recess, 11... Inner periphery, 12... Bottom, 13... Edge, 2... Protrusion, 21... Gap, 3
...Attachment and removal groove, 4...Semiconductor wafer, 41...Orientation flat.

Claims (1)

【実用新案登録請求の範囲】 半導体ウエーハのナンバリングのために半導体
ウエーハをセツトする台座であつて、半導体ウエ
ーハをセツトするためにこの半導体ウエーハの直
径よりわずか大きい直径で、この半導体ウエーハ
の厚さとほゞ同一の深さの円板状の窪みがあり、
この円板状の窪みの外周部に前記半導体の着脱を
容易にするピンセツト挿入用の着脱溝を備えた半
導体ウエーハのセツト用台座において、 半導体ウエーハがセツトされる円板状の窪みの
内周部に、前記半導体ウエーハの方向きめのオリ
エンテーシヨンフラツトに対向してこのオリエン
テーシヨンフラツトとの間にわずかに隙間を有す
る突起を設けるとともに、前記窪みの底面部を中
央部が深い球面で形成する ことを特徴とする半導体ウエーハのナンバリング
用台座。
[Claims for Utility Model Registration] A pedestal on which a semiconductor wafer is set for numbering the semiconductor wafer, the pedestal having a diameter slightly larger than the diameter of the semiconductor wafer and having a diameter approximately equal to the thickness of the semiconductor wafer. There is a disc-shaped depression of the same depth,
In the pedestal for setting a semiconductor wafer, which has an attachment/detachment groove for inserting tweezers to facilitate attachment and detachment of the semiconductor on the outer periphery of the disk-shaped depression, the inner periphery of the disk-shaped depression in which the semiconductor wafer is set. A protrusion is provided opposite to the orientation flat for determining the direction of the semiconductor wafer and has a slight gap between the protrusion and the orientation flat, and the bottom of the recess is formed with a deep spherical surface in the center. A pedestal for numbering semiconductor wafers.
JP2190089U 1989-02-27 1989-02-27 Pending JPH02113329U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2190089U JPH02113329U (en) 1989-02-27 1989-02-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2190089U JPH02113329U (en) 1989-02-27 1989-02-27

Publications (1)

Publication Number Publication Date
JPH02113329U true JPH02113329U (en) 1990-09-11

Family

ID=31239537

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2190089U Pending JPH02113329U (en) 1989-02-27 1989-02-27

Country Status (1)

Country Link
JP (1) JPH02113329U (en)

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