JPS6310060U

JPS6310060U -

Info

Publication number: JPS6310060U
Application number: JP1986103930U
Authority: JP
Priority date: 1986-07-07
Filing date: 1986-07-07
Publication date: 1988-01-22

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例の分解斜視図、第２
図はその要部の縦断面図、第３図は従来例の縦断
面図である。１……研磨治具、３……底板、５……テンプレ
ート、６……位置決め穴。 Fig. 1 is an exploded perspective view of one embodiment of the present invention;
The figure is a vertical cross-sectional view of the main part, and FIG. 3 is a vertical cross-sectional view of a conventional example. 1... Polishing jig, 3... Bottom plate, 5... Template, 6... Positioning hole.

Claims

[Claims for Utility Model Registration] (1) A bottom plate and a template through which a positioning hole for positioning a workpiece is formed are laminated and fixed to each other, and the bottom plate is fixed at least in a portion constituting the bottom of the positioning hole. A polishing jig for semiconductor wafers, etc., characterized in that it is configured to have a surface friction coefficient of . (2) A polishing jig for semiconductor wafers, etc., as set forth in claim 1, which has a surface friction coefficient of 0.1 or more. (3) The polishing jig for semiconductor wafers, etc. according to claim 1, wherein the bottom plate is formed of a member having a surface friction coefficient of 0.1 or more. (4) The bottom plate is formed of a member having a surface friction coefficient of less than 0.1, and a raised portion formed by glow discharge or sputter etching is provided on at least the surface of the portion constituting the bottom of the positioning hole. A polishing jig for semiconductor wafers, etc., as set forth in Claim 1 of the Utility Model Registration Claim. (5) The above-mentioned bottom plate is formed of a member having a surface friction coefficient of less than 0.1, and the surface of at least the bottom of the positioning hole has irregularities formed by etching. A polishing jig for semiconductor wafers, etc. according to scope 1.