JPH02110792A - Microcomputer - Google Patents

Abstract

PURPOSE:To set plural modes with a single test terminal by setting three or more modes by discriminating the combination between the level of a reset terminal and the level of the test terminal. CONSTITUTION:The title microcomputer is composed of a microcomputer body 1, a gram counter 2, an internal ROM 3, an instruction register 4, an instruction decoder 5, an initializing circuit 6, a mode setting circuit 7 to output a control signal to the initializing circuit 6 and set various modes, an internal bus 8, a reset terminal 9, a test terminal 10, ports 11-13, and an external ROM. Further, three or more modes are set by discriminating the combination of the levels to be impressed to the reset terminal 9 and the test terminal 10 from an external part. Thus, plural modes can be set only by equipping the microcomputer with the single test terminal.

Description

Detailed Description of the Invention (a) Industrial Application Field The present invention relates to a one-chip microcomputer that can set external memory mode, internal memory mode, test mode, etc. using a single terminal. .

(b) Conventional technology A one-chip microcomputer (hereinafter simply referred to as a microcomputer) that incorporates a program memory as a mask ROM starts executing the program memory when the power is turned on. Therefore, in order to perform product tests to determine whether the program memory stores programs correctly or whether the various functions of the microcomputer operate normally, it is necessary to control the execution of the program memory. It becomes necessary. In addition, a microcomputer that allows expansion of program memory and data memory also requires control terminals for this purpose.

In order to set these three to four modes, microcontrollers have been equipped with two terminals: one for switching between internal ROM mode and external ROM mode, and the other for switching between execution mode and test mode. Computer,
Alternatively, a single test terminal can be used as a ternary input (e.g. OV, 5
V, 10V), and three types of modes are known depending on the level of the test terminal. However, the former has the disadvantage that the number of ports is limited due to the increase in the number of control terminals, and the latter This has the drawback that it requires a circuit with a high input level and also requires a high breakdown voltage.

(c) Problems to be Solved by the Invention The present invention has been made in view of the above points, and an object thereof is to provide a microcomputer that can set multiple modes using a single test terminal. be.

(2) Means for Solving the Problems This invention sets three or more modes by determining the combination of the level of the reset terminal and the level of the test terminal, or by determining the change in the level of the test terminal and the initial level of the test terminal. It is characterized by the fact that

(e) Operation The above configuration operates so that a plurality of modes can be set by inputting an ordinary signal to a single test terminal.

(f) Embodiment FIG. 1 is a block diagram of an embodiment of this invention.
) is the microcomputer body, (2) is the program/
counter (hereinafter referred to as PC), (3) is an internal ROM,
(4) is an instruction register, (5) is an instruction decoder, (6)
is an initialization circuit, (7) is a mode setting circuit that outputs a control signal to the initialization circuit (6) and sets various modes, (8) is an internal bus, (9) is a reset terminal, (10)
are test terminals, (11) to (13) are ports, (14)
is an external ROM. In addition, the microcomputer main body (
The external circuit 1) shows one connection example.

Each mode will be explained below with reference to the timing chart of FIG.

[1] Internal ROM execution mode: When a power-on reset is performed with the test terminal (10) grounded, the instructions in the internal ROM (3) can be executed. A timing chart is shown in FIG. 2(a).

When the "L" level output TEST' of the input buffer CP, which inputs the "L" level TEST, is input to the mode setting circuit (7), the AND gate AN and A N a are turned off, and inverted by the inverter IN. *TEST
becomes “H” level. In addition, the reset terminal voltage RES
rises and reaches the input buffer threshold voltage V 1 k l at time T, the input buffer CP outputs *RES' at the B IT level. This *R
RES, which is obtained by inverting ES' by the inverter IN, becomes the ``I, +t level after time T, turning off the AND gate AN and ANs.
AND gate A N that inputs S and *T E S T
The output R8T of t rises at time T when vo rises and falls at time T2. This R8T is input to the reset terminal of the RS flip-flop FF, and it is reset at the rising edge of R8T, and the output is “H”.
Further, the PCINT output of the OR gate OR which inputs the Q output of is set to the "H" level. “H
” level PCINT turns on the AND gate AN,
and gate AN controlled by inverter INK,
Turn off. Furthermore, R8T is also input to the initialization circuit (6), and the initialization circuit (6) inputs R8T for a predetermined period of time.
When the H1 level is continued, the PSW, PC, and registers are initialized.

On the other hand, *RES' and “LIT level TEST”
The output IRINT of the exclusive OR gate EOR to which
It is at "L" level at *, and becomes "H" level from time T onwards. Then, at time T, from then on, the I R is at "H" level.
I NT turns on the AND gate A N a , and the AND gate A N a controlled by the inverter IN turns on.
s is off.

Therefore, when the microcomputer is initialized at time T, the internal ROM (3) is sequentially accessed from address 0 by the PC (2), and its instructions are passed through the AND gate A N
4. Instruction decoder (5) via instruction register (4)
transferred to and executed.

[2] Internal ROM read mode: By grounding the reset terminal (9) and applying an "H" level to the test terminal (10), data in the internal ROM (3) is output to the port. A timing chart is shown in FIG. 2(b).

Since the TEST terminal (10) is at the "H" level, the output TEST' of the input buffer CP is at the "H" level, and the grounding of the reset terminal (9) causes the RES and *RE
S' becomes L" level. Then, the output RES of inverter IN which inputs *RES' becomes H" level, and AND gate A which inputs RES and TEST'
Ns outputs a ROMRD signal of "HIT level.

When ROMRD becomes “H” level, the instruction decoder (5
> decoding is prohibited and AND gate AN is turned on. Furthermore, a control circuit (not shown) controls the PC (2
), the internal ROM (3) is accessed in order from address 0, and all data in the internal ROM (3) is accessed via the instruction register (4) and internal bus (8) to a predetermined port (13) without being decoded. ).

[3] External ROM execution mode: When a power-on reset is performed with the test terminal (10) connected to the reset terminal (9), PC data is output from a predetermined port, and the external ROM that is accessed by it is output. The instruction (14) is executed. The timing chart is shown in Figure 2 (c
).

Threshold voltage vlbI of input buffer CP□, CP.

V t h I> V t h *
2 setting tL theory, sono output *RE S' and TE
ST' rises at a time Tt+Ts with a slight time difference.

AND gate A which inputs RES and *TEST which are inverted by inverters IN, IN, respectively.
The output R8T of N is the time TI when the power supply voltage v0 rises.
It rises at TEST' and falls at the time T at which TEST' rises. This R8T resets the RS flip-flop FF, sets its Q output to "H", and also sets the initialization circuit (6
) is entered.

Now, at time T, the microcomputer completes its initialization and starts operating based on the internal clock. However, at time T, the microcomputer, for example, PC (2)
Set the data in the PC register (not shown), and
The data in 2) is incremented by 1. Therefore, *R
Even if the exclusive OR gate EOR inputting ES' and TEST' outputs IRINT at "H" level between Tt and Ts, IRINT can realistically be considered to be at "L11 level". .Then, the L” level I R
The AND gate AN4 is turned off by INT, and the AND gate AN controlled by the inverter N4 is turned on.

Also, the inversion of inverter IN, *RES' and TES
The AND gate A N * to which T' is input is Tt T
It outputs a pulse that becomes "H" for s and sets the RS flip-flop FF. This causes the Q output to be “L”
Therefore, the output PCINT of the OR gate OR becomes "L" level from time T onwards. And “L” level PCI
Ant game) AN is turned off by NT, and inverter I
The AND gate A N a controlled by N is turned on.

Therefore, initialization ends at time T, and P
The data of C(2) is applied to the AND gate A N a at time T.
It is output to port (11) via. Then, the external ROM (14) is accessed in order from address 0,
The instruction is port (12), AND gate A N a,
It is set in the instruction decoder (5) via the instruction register (4) and executed.

[4] External command application test mode: Test terminal (1
By power-on resetting with 0) grounded and then setting the test terminal (lO) to H" level, the tester's commands unrelated to the data on the PC (2) are executed. See the timing chart below. It is shown in FIG. 2(d).

As TEST' rises later than *RES,
The AND gate AN inputting the inverted *RES and TEST' of the inverter INg never outputs the "H" level. Therefore, the RS flip-flop FF remains reset by the rise of R8T, and its Q output remains at the "H" level. On the other hand, the output I R of the exclusive OR gate EOH which inputs TEST' and *RES
INT is the rising time T of TEST', and thereafter it is L”
level.

Therefore, after starting up the test terminal (10), the tester (
By outputting an instruction to a port (12) from a port (not shown), the instruction is set in an instruction decoder (5) via an AND gate A N 6 and an instruction register (4), and is executed.

The truth values in each mode are shown in the table below.

Next, a modification of the mode setting circuit will be explained with reference to FIG.

This mode setting circuit determines whether the level of the test terminal (10) is "H" level at the rise of R8T or not.
The various modes are determined based on whether the test terminal (10) is at "level" and whether the level of the test terminal (10) changes from "L91" to "H". Each mode will be explained below.

[1] Internal ROM execution mode: The internal ROM is executed by power-on reset with the test terminal (10) grounded. The timing chart is 4th
Shown in Figure (a).

The D flip-flop FF latches R8T ``H'' at the positive edge of the system clock. That is, D flip-flop FFI delays the positive edge of vo by one system clock. This Q output is D
It is input to the trigger terminal φ of the flip-flop FF, and the flip-flop FF2 latches the output of the input buffer CP at the rising edge of the Q output of the flip-flop FF. The output TEST' of the input buffer CP t is continuously at the "L" level, and the flip-flop FF preserves the "L" level, and the RO is at the "L" level.
Output MRD. In addition, the inverter IN+t that inverts TEST' outputs an H" level, and the OR gate OR,
, via “H1 Lebel’s I RI NT and PCI
Generate NT.

[2] Internal ROM read mode: By performing a power-on reset with the test terminal (10) set to the "H" level, the data in the internal ROM (3) is output to the port. A timing chart is shown in FIG. 4(b).

Since the test terminal (10) is at "H" level at reset, the D flip-flop F F which generates ROMRD
t latches "H" level TEST' and generates "HII level ROMRD. Then, by the OR gate OR, which inputs this, "H1 level I RI N
Generate T and PCINT.

[3] External ROM execution, external command application mode: When a power-on reset is performed with the test terminal (10) connected to the reset terminal (9>), the PC is
The data is output, and the command of the external ROM (14) accessed by the data is executed.

The timing chart is shown in FIG. 4(c).

The D flip-prop FF latches the initial level “L” of the test terminal (10), and the ROMRD latches the “L” level of the test terminal (10).
It is I level. m value V of input buffer cp, , cp,
lb+, Vlbald Vth+>V+h* is set, and when RES rises, input buffer CP turns on at time T, followed by time T.

The input buffer CPI is turned on. Therefore, the output of the inverter 11'J+th is the time T when the initialization is completed,
At the previous time T, the level changes from the HIT level to the "L" level. As a result, the OR gate OR is set to “L” level I
Generate RI NT and PCINT.

The truth values in each mode of the modified example are shown in the table below.

(G) Effects of the Invention As described above, according to the present invention, it is possible to provide a microcomputer that is equipped with only a single test terminal and can set multiple modes by inputting extremely ordinary signals. .

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG.
), (b), (c), and (d) are timing charts at the time of executing the internal ROM, reading the internal ROM, executing the external ROM, and applying an external command, respectively. Figure 3 is a modified example of the mode setting circuit. The block diagram of FIGS. 4(a), 4(b), and 4(c) are timing charts at the time of executing the internal ROM, reading the internal ROM, executing the external ROM, and applying an external command in the modified example, respectively. (1)...Microcomputer, (2)...Program counter, (3)...Internal ROM, (4)...
・Instruction register, (5)...Instruction decoder, (6)
...Initialization circuit, (7)...Mode setting circuit,
(8)...Internal bus, (14)...External ROM. 2nd rIA (c) Figure 2 (0) House RES' Figure 2 (b) ↑1 z T3 Figure 2 (d) Figure 3 Figure 4 (0) CINT Figure 4 (b) Figure 4 ( C) OMRD mTNT 1f-1111]

Claims (5)

[Claims] (1) In a microcomputer with a built-in program memory that permanently stores programs, a mode setting circuit connected to a reset terminal and a test terminal is provided,
A microcomputer characterized in that three or more modes are set by determining a combination of levels applied externally to the reset terminal and the test terminal. (2) A microcomputer according to claim 1, wherein a plurality of modes are set by changing the level of the test terminal and determining the initial level of the test terminal. (3) Comparators that discriminate between the reset terminal voltage and test terminal voltage, exclusive OR gates that input the respective comparator outputs, and a comparison that discriminates between the inverted output of the comparator that discriminates the reset terminal voltage and the test terminal voltage. The internal ROM and external ROM are selected by the exclusive OR gate, and the data of the program counter is selected and output to the port by the OR logic signal of the exclusive OR gate and the flip-flop output. 2. The microcomputer according to claim 1. (4) means for selectively inputting internal ROM data and external ROM data to an instruction register based on the test terminal level and the initial level of the test terminal; means for selectively outputting PC data to the port based on the test terminal level; 2. The microcomputer according to claim 1, further comprising means for selectively outputting the data of the instruction register to the port based on the initial level of the test terminal. 5. The microcomputer according to claim 1, wherein one of the modes is selected by connecting the test terminal to the reset terminal.