JPH02110785A - Mask data processing system - Google Patents

Abstract

PURPOSE:To connect a general purpose processor to a high speed data bus and to construct an inexpensive picture processor without lowering its performance by writing only a part of picture data having a mask bit, in which the mask bit is under an OFF state, through the high speed data bus to a picture memory correspondingly to the sending of the picture data by the processor. CONSTITUTION:When a write inhibiting signal is sent when the mask bit in the picture data having the mask bit is under an ON state correspondingly to the sending of the picture data by a processor 1, and when a picture memory control circuit 5 receives the ON-state with inhibiting signal, the circuit 5 inhibits a write enable signal to write the picture data transferred through a high speed data bus 4 to the prescribed address of a picture memory 6. Consequently, the processor 1 can write only the arbitrary area of the picture data, which is not masked, through the high speed data bus 4. Thus, the general purpose processor can be connected to the high speed data bus, and the inexpensive picture processor can be constructed without lowering its performance.

Description

[Detailed Description of the Invention] [Summary] Regarding a mask data processing method that controls writing to an image memory using mask data, in response to a processor sending out image data having mask bits, A processor that performs image processing with the aim of connecting a general-purpose processor to a high-speed data bus and building an inexpensive image processing device without degrading performance by writing only the portion where the mask bit is off to the image memory. and an interface circuit that receives image data with a mask bit sent from this processor, sends the image data to a high-speed data bus, and also sends out a write prohibition signal when the mask bit is on, and the high-speed data from this interface circuit. The image data sent to the bus and the above-mentioned line prohibition signal are captured, and when this write prohibition signal is off, this image data is written to the image memory and the address is updated. On the other hand, when the line prohibition signal is on, the image data is It is equipped with an image memory control circuit that updates addresses without writing, and is configured to prohibit writing to the image memory only when the mask bit is on in response to the processor sending out image data with a mask bit. Configure.

[Industrial application field]

The present invention relates to a mask data processing method that controls writing to an image memory using mask data. In particular, the present invention relates to a method for controlling the writing range using mask data when a processor writes image data to an image memory via a high-speed data bus.

[Prior art and problems to be solved by the invention] Conventionally, image processing devices require high-speed data transfer, and image processing is often performed in a rectangular range, so an address bus is not provided. Only a high-speed data bus is provided in the image memory control circuit, and image memory addresses are generated in the image memory control circuit. Such an image processing apparatus can perform extremely high-speed image processing by using dedicated hardware as a processor that processes only image data, and can relatively easily implement control of writing to the image memory using a mask. Such dedicated hardware is expensive, requires hardware for each process, and has the problem of increasing scale.

Therefore, in recent years, it has been desired to perform image processing at low cost by using general-purpose microprocessors that are becoming faster.

However, since general-purpose microprocessors perform mask processing using software, there is a problem in that they cannot control writing to the image memory on a high-speed data bus that does not have an address bus.

The present invention enables a general-purpose processor to transmit high-speed data by writing only the part where the mask bits are off to the image memory via a high-speed data bus in response to the processor sending out image data with mask bits. The aim is to build an inexpensive image processing device that can be connected to a bus without sacrificing performance.

[Means to solve problems]

Means for solving the problem will be explained with reference to FIG.

In FIG. 1, a processor 1 performs image processing.

The interface circuit 3 receives image data with mask bits sent from the processor 1, sends the image data to the high-speed data bus 4, and also sends out a write inhibit signal when the mask bits are on.

The high-speed data bus 4 is a data bus that transfers image data at high speed.

The image memory control circuit 5 supplies a write enable signal to the image memory 6 for portions of the image data transferred via the high-speed data bus 4 for which the line prohibition signal is not on, and controls writing the image data to the corresponding address. It is something to do.

The image memory 6 stores image data.

[Effect]

As shown in FIG. 1, in the present invention, an interface circuit 3 that receives image data having a mask bit from a processor 1 sends the image data to a high-speed data bus 4, and when the mask bit in this image data is on. A write enable signal for writing the image data transferred via the high-speed data bus 4 to a predetermined address in the image memory 6 when the image memory control circuit 5 receives the ON write prohibition signal. We are trying to ban it.

Therefore, the processor 1 can write image data only in an arbitrary non-masked area via the high-speed data bus.

〔Example〕

Next, the configuration and operation of one embodiment of the present invention will be explained in detail using FIGS. 1 to 3.

In FIG. 1, a processor 1 performs image processing, and is a general-purpose 32-bit microprocessor or the like.

The decoder 2 decodes the address signal sent from the processor 1 to the address bus, and decodes the address signal sent from the processor 1 to the interface circuit 3.
When accessed, an ENABLE signal is output. The interface circuit 3 uses this ENABLE
It becomes active when a signal is input, and processor 1
It receives image data sent to the data bus from the data bus 4, sends the image data to the high-speed data bus 4, and sends out a write prohibition signal when the mask bit in the image data is on.

The high-speed data bus 4 is a data bus that transfers image data at high speed between the interface circuit 2 and the image memory control circuit 5.

The image memory control circuit 5 receives image data transferred via the high-speed data bus 4, automatically generates an address, and writes this image data into the image memory 6. At this time, if a write prohibition signal is received, the sending of the write enable signal is stopped to prevent writing to the image memory 6, and mask processing is performed.

The image memory 6 stores image data.

Next, the operation of the configuration shown in FIG. 1 will be explained in accordance with the order shown in the flowchart of FIG.

In FIG. 2, ■ sets the processing image segment. This means setting which processed image segment the processor 1 will perform image processing on. This setting is performed by setting the start address, end address, data length per pixel (1 to 32 bits), etc. in the register of the image memory control circuit 5.

■ Configure the mask.

■Sets the mode. This means that mode settings such as whether to set the mask mode related to this embodiment are performed. In some cases, all bits of the data bus are used as image data without setting the mask mode according to this embodiment.

(2) The processor 1 reads the processed image and mask data.

In (2), the processor 1 performs image processing such as density conversion.

(2) merges mask bits and image data.

For example, as shown on the right, 1 byte of R, G,
This means that the image data consisting of B and the mask bit consisting of one hit are merged as shown.

(2) The CPU (processor 1) outputs image data to the data bus.

(2) The interface circuit 3 takes in the most significant bit (-mask bit) and creates a write prohibition signal. This means that when the mask bit is "1", the interface circuit 3 that received the image signal merged in (3) creates a write prohibition signal and notifies the image memory control circuit 5. Interface A specific example of the circuit 3 will be explained with reference to FIG.

The interface circuit 3 includes a register R1 in which data from the data bus is set, a register R2 in which a mask bit is set, a register R3 for delaying and outputting the output of the register R1, a flip-flop holding an enable signal, and a hash. It is composed of drivers B1, B2, and B3.

To explain the operation, when processor 1 accesses interface circuit 3, ENABL is sent from decoder 2.
The E signal is input to the interface circuit 3. When the interface circuit 3 receives this ENABLE signal,
Data is placed in register R1, and mask bits are placed in register R2. A write inhibit signal is immediately output from the register R2 via the driver B3.

On the other hand, the output of register R1 is sent to high-speed data bus 4 after being sent to register R3 again.

(2) prevents the memory control circuit 5 from outputting the write enable signal to the image memory 6 when the write prohibition signal is "'1".This means that when the memory control circuit 5 receives the write prohibition signal, the write enable signal is not output. This means that only the address is updated without sending the address to the image memory 6. On the other hand, when the write inhibit signal is O'', the image memory control circuit 5 inputs the address to the image memory 6 and also updates the write enable signal. is input, the image data transferred via the high-speed data bus 4 is written, and the address is updated. Here, the memory control circuit 5
A specific example is shown in FIG. The memory control circuit 5 includes a delay circuit 51. Nant gate 52, receiver 53, address counter 54, AND gate 55, register 56.5
7.

Data from the high-speed data bus 4 is given to the image memory 6 via the receiver 53,
Writing is performed according to the address from. but,
When the write prohibition signal is being output, the Nant gate 52 does not output the write enable signal WE, so writing to the screen memory 6 is prohibited. Further, the address counter 54 starts counting from the value corresponding to the start address set in the register 56 and continues counting up to the value corresponding to the stop address set in the register 57.

Therefore, only the circled part of the image data of Mt. Fuji in Figure 3 (b) is displayed in the background with people in Figure 3 (a).
When writing as shown in the circled area in Figure (a), the processor 1 writes the entire image data of Mt. Fuji in Figure 3 (b) and the mask bits corresponding to the mask data in Figure 3 (c) to this image data. By simply adding the data to the interface circuit 3 and sequentially sending it to the interface circuit 3 pixel by pixel, only the unmasked circular portion can be written into the image memory 6 via the high-speed data bus 4, as shown in FIG. 3(a). becomes.

〔Effect of the invention〕

As described above, according to the present invention, in response to the processor sending out image data having a mask bit, the processor sends the image data to the high-speed data bus, and also sends a write prohibition signal when the mask bit is on. Since the image data for which this line inhibit signal has been sent is not written to the image memory and the address is updated, it is possible to connect a general-purpose microprocessor to a high-speed data bus without degrading performance. , it is possible to quickly write image data in areas that are not masked. This makes it possible to construct an inexpensive image processing device using the microprocessor sensor.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of one embodiment of the present invention, FIG. 2 is a flowchart explaining the operation of the present invention, and FIG. 3 is a diagram explaining the operation of the present invention.
FIG. 4 shows a specific example of the interface circuit, and FIG. 5 shows a specific example of the image memory control circuit. In the figure, 1 is a processor, 3 is an interface circuit, 4 is a high-speed data bus, 5 is an image memory control circuit, and 6 is an image memory.

Claims (1)

[Claims] A mask data processing method that controls writing to an image memory using mask data includes a processor (1) that performs image processing, and a processor (1) that receives image data having mask bits sent from the processor (1). , an interface circuit (3) that sends image data to the high-speed data bus (4) and also sends out a write prohibition signal when the mask bit is on;
), and when this write prohibition signal is off, this image data is written to the image memory (6) and the address is updated; on the other hand, when the write prohibition signal is on, An image memory control circuit (5) that updates addresses without writing image data, and in response to the processor (1) sending out image data with a mask bit, the image memory control circuit (5) updates the address only when the mask bit is on. A mask data processing method characterized in that it is configured to prohibit writing to a memory (6).