JPH1124689A - Effective sound processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the generation of unnecessary signals, abrupt change in a signal level, sound cutoff, etc., in switching an input aural signal, by stopping the addition of readout data of a RAM for a prescribed time in a timing generation such as switching of the input aural signal and changing of effective sound processing mode. SOLUTION: A second register 4 between a RAM and an adding part 3 is provided with switch mechanism which is controlled by a time flag 7. A timer counter 8 sets a prescribed time in switching an input aural signal and changing a lag time so that the timer flag 7 prevents the readout data of the RAM 2 from being transmitted to the adding part 2 during the set time. That is to say, the input aural data of a first register 3 is outputted from a third register 6 via the adding part 2 during this interval. This constitution can eliminate any effects of the readout of the RAM 2 data which is irrelevant to the input signal so as to provide a superior aural signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for performing sound effect processing on digitized audio data by delay.

[0002]

2. Description of the Related Art In order to perform sound effect processing (effect processing) such as a delay that causes blurring of sound, an echo or reverb that produces continuous sound like Yamahiko, and a surround that expands sound, digital audio data is used. Delaying by a predetermined time is performed.

[0005] In such a process, as shown in FIG.
A RAM 2 is connected to a DSP (Digital Signal Processor) 1 for an audio signal (or an internal RAM is used), and the audio data written in the RAM 2 is read out after a predetermined time has elapsed, so that the audio data is read out. Have been delayed.

FIG. 6 shows an RA for explaining the delay processing.
FIG. 3 is a diagram illustrating an address space of M2. In this delay processing, when audio data is written in order from the address “0000” and is written up to “FFFF”, “000” is again written.
On the other hand, reading is performed for an address shifted (delayed) by a predetermined address from the current writing address while the data is overwritten from “0”. For example, 10-40m in delay
s and echo are delayed by 50 ms or more), and data is delayed by the time difference.

For example, if the current write address is A1
If the current read address is A2 (note that writing and reading are performed at different timings, but the time difference is significantly shorter than the sampling period of the audio data, so it can be regarded as simultaneous). , And the delay time Td is as follows: Td = (A1−A2) * t t is a sampling period of audio data. The delay time is set by setting the address difference between writing and reading in this way.

When this is applied to delay processing, the signal flow can be represented as shown in FIG. Reference numeral 3 denotes a first register for temporarily holding input audio data, 4 denotes a second register for temporarily holding read data from the RAM 2, 5 denotes an adder for adding data of the registers 3 and 4, and 6 denotes an adder. A third register that temporarily holds the data added by the unit 5 and outputs the data as output audio data; DS is stored in the first to third registers 3, 4, and 6.
The register in P1 is used. Further, the adder 5 is provided with a DS
At P1, it is realized by software.

FIG. 8 is a flowchart showing sound effect processing per sampling period. In step S1 ', delay, echo, reverb, surround, and other sound effect processing shown in FIG. 7 are performed. In step S2,
Refresh the RAM 2 (necessary when the RAM 2 is a DRAM) and perform other processing.

By the way, in the above-described sound effect processing device, the input audio signal is switched (source switching).
To change the sound effect mode for switching the contents of the sound effect processing (delay, echo, reverb, surround, etc.), the read time of the RAM is changed to change the delay time.

Conventionally, no processing is performed for such input voice signal switching or delay time change, or the data between the write and read addresses is written to the RAM 2 only at this time. Cleared and corresponded.

[0010]

However, when the input audio signal is simply switched, uncorrelated delay data is read out and added to the input audio data, so that an unnecessary signal (noise) or a sudden In a system that causes a change in signal level or clears the RAM 2, a sound break occurs only during that period. Also, while the RAM is being cleared, no control signal can be received from the outside.
There is a problem that it is difficult to create a control program for P.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has as its object the purpose of switching input audio signals and changing
An object of the present invention is to prevent the occurrence of unnecessary signals, abrupt changes in signal level, and interruptions in sound when changing the read address of AM.

[0012]

According to a first aspect of the present invention, there is provided an output audio data subjected to sound effect processing by adding input audio data delayed by a RAM to current input audio data. In the sound effect processor,
A control means is provided for stopping the addition of the read data from the RAM for a predetermined time when a timing such as switching of the input audio signal or change of the sound effect processing mode occurs. According to a second aspect, in the first aspect, the control means includes a timer means for setting a timer time when the timing is generated, and a switch means for clearing data read from the RAM to zero while the timer time is set by the timer means. It was comprised so that it might have.

[0013]

FIG. 1 is a diagram showing a signal flow of delay processing according to one embodiment of the present invention. In this embodiment, the second register 4 between the RAM 2 and the adder 3 has a switch function, and the switch function is controlled by the timer flag 7. Reference numeral 8 denotes a timer counter that controls the timer flag 7. The timer flag 7 and the timer counter 8 use those in the DSP 1 or are realized by software.

That is, in this embodiment, the timer flag is set to "1" and the timer counter 8 is set in the timer counter 8 when the input audio signal is switched or when the delay time is changed by changing the read address of the RAM. A predetermined value is set, and while the timer flag 7 is being set, the second register 4 has a "switch-off function" so that the read data of the RAM 2 is not added by the adder 5.

The details will be described below. FIG. 2 is a flowchart for performing an interrupt when the above-mentioned timing occurs in order to perform such processing. Here, a control signal is generated when a timing occurs, such as when the input audio signal is switched or when the delay time is changed, and an external interrupt is applied to the sound effect processing step S1. Thereby, step S
In 3, the value corresponding to the difference between the write address and the read address described with reference to FIG.
Set to "1". In step S4, control processing of input signal switching and sound effect mode switching according to the control signal is performed.

FIG. 3 is a modified version of step S1 'in the flowchart shown in FIG. 8, which is replaced with step S1 incorporating step S11 for performing the processing shown in FIG.
Hereinafter, the switching process will be described with reference to the flowchart of FIG. If the "timer flag is not 1", the determination in step S111 is N, and the second register 4 is in the "switch-on function" state,
The normal operation of transferring the read data of No. 2 to the adder 5 is performed.

If "timer flag = 1" is set in step S3 of FIG. 2, the determination in step S111 becomes Y, so that the content (RAMout) of the second register 4 is cleared in the next step S112. . As a result, the transfer data from the RAM 2 to the adder 5 is “0”.
(No data). That is, the second register 4 is in the state of the “switch-off function”. In this case, in step S113, "N" set in the timer counter 8 is decremented by one. If the result is not “N = 0”, the determination in step S114 is N.

The above processing is repeatedly performed for each sampling time of the audio data, and the decrement of “N” set in the timer counter 8 progresses, and “N = N”
When it becomes “0”, the determination in step S114 becomes Y, so in the next step S115, “timer flag =
"0" is set. After this, step S111
Becomes N, and the process of step S112 is not performed, so that the second register 4 enters the “switch-on function” state, and starts the normal operation of transferring the read data from the RAM 2 to the adding unit 5.

As described above, in this embodiment, when the input audio signal is switched or the delay time is changed, a predetermined time is set by the timer counter 8, and during this set time, the read data of the RAM 2 is set by the timer flag 7. Is not transferred to the adder 2. That is, during this period, only the input audio data from the first register 3 is output from the third register 6 via the adder 2, so that it is not affected by the data read from the RAM 2.

In the above example, the timer counter 8
Is set according to the "difference" between the read address and the write address of the RAM 2, but this "N" corresponds to a time longer than the time required for the input signal switching process and the delay time setting change process. Any value is acceptable.

[0021]

As described above, according to the present invention, the RAM which is uncorrelated with the input signal immediately after switching the input signal or changing the delay processing mode during the delay processing.
Since the influence of data reading can be eliminated, a good audio signal can be obtained. Also, the creation of the DSP processing program can be simplified because restrictions on command timing and the like can be reduced.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a signal flow of delay processing according to an embodiment of the present invention.

FIG. 2 is a flowchart for explaining an interrupt to the sound effect processing according to the embodiment;

FIG. 3 is a schematic flowchart of sound effect processing according to the embodiment.

FIG. 4 is a flowchart of switch control.

FIG. 5 is a block diagram illustrating a hardware configuration of sound effect processing by a DSP.

FIG. 6 is an explanatory diagram of a memory space of a RAM for explaining a delay process.

FIG. 7 is an explanatory diagram of a signal flow of conventional delay processing.

FIG. 8 is a schematic flowchart of conventional sound effect processing.

[Description of References] 1: DSP, 2: RAM, 3: first register, 4: second register, 5: adder, 6: third register, 7:
Timer flag, 8: Timer counter.

Claims (2)

[Claims] 1. A sound effect processing device for obtaining output sound data subjected to sound effect processing by adding input sound data delayed by a RAM to current input sound data. A sound effect processing device comprising a control means for stopping the addition of the read data from the RAM for a predetermined time when a timing such as a change occurs. 2. The control means comprises: timer means for setting a timer time when the timing occurs; and switch means for clearing the data read from the RAM to zero during the timer time setting of the timer means. The sound effect processing device according to claim 1.