JPH02278341A - Interruption control circuit - Google Patents

Abstract

PURPOSE:To attain restoration in such a way that the interruption request of low priority is automatically processed and a processing is executed from the interruption request of high priority by installing the counter of an interruption request signal pulse and a comparator or the like outputting the coincidence signal of a content with a register to which data can be written from an internal bus, and monitoring the number of pulses of an interruption request signal. CONSTITUTION:The counter 1 counts the signal pulses inputted to an interruption request signal line iRn. The contents of the counter 1 and the register 2 are inputted to the comparator 4 and compared. When both contents agree, a logic '1' is outputted to a coincidence line 5, the data is held in a latch 6. Then, a control signal line 7 zero-clears the counter 1 and a control signal line 7' masks all the outputs of the interruption request register 10 of iR0 to iRn-1. Consequently, highest priority is given to iRn at that time, and the interruption processing starts. Then, a system is restored to normal priority when the interruption processing routine terminates. Thus, the interruption request of low priority can automatically processed even if the interruption request of high priority is always and continuously inputted.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an interrupt control circuit.

[Conventional technology]

A conventional interrupt control circuit will be described in detail with reference to the drawings.

FIG. 3 is a block diagram showing an example of a conventional interrupt control circuit.

There are usually a plurality of interrupt request signals 11, each of which is connected to a device, etc., and the interrupt request from each device is stored in the interrupt request register 10.

When multiple interrupt requests occur, the priority determination logic 9 determines the priority given to each bit at the time of initialization, and selects which bit based on the mask bit information stored in the interrupt mask register 14. Decide whether to process with top priority.

An interrupt request to the microprocessor 101 is notified by an interrupt signal 109 via the control logic 104.

When the microprocessor 101 determines that the interrupt can be accepted, it outputs an interrupt acknowledge signal 108 to the interrupt control circuit 100.

Upon receiving the interrupt acknowledge signal 108, the interrupt control circuit 100 transfers the data bus 1 from the data bus buffer 103.
12, the interrupt routine address with the highest priority at that time is output and notified to the microprocessor 101.

FIG. 4 is a circuit diagram showing one bit of the interrupt request register shown in FIG. 3.

The edge detection circuit 118 detects the rising edge of the interrupt request signal [1] for 1 bit of the interrupt request input section, latches it in the interrupt request register 10, and sends it to the control logic 104.
will be notified.

FIG. 5 is a time chart for explaining the operation of the interrupt control circuit shown in FIG. 3.

[Problem to be solved by the invention]

The conventional interrupt control circuit described above is designed to process interrupt requests starting from the highest priority, so if interrupt requests with high priority are input continuously, This has the disadvantage that interrupt requests with a low value will not be processed forever.

[Means to solve the problem]

The interrupt control circuit of the present invention includes a counter that counts interrupt request signal pulses, a register that can be written from an internal bus, and a match signal that is output when the contents of the counter and the register are compared. and a latch that holds the coincidence signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

The counter 1 counts the interrupt request signal 11 and can be cleared to zero.

The register 2 is writable from the internal bus 3.

Comparator 4 compares the contents of counter 1 and register 2, and if they match, outputs logic "1°'" and i
The signal is input to the latch 6 via the transfer 12 controlled by the NTA.

The control signal line 7 is ANDed with the zero clear signal of the counter 1, and the control signal line 7' is ANDed with the output line 8 of the interrupt request register 10 (excluding iRn), and the priority determination logic 9 is input.

Next, the operation will be explained.

Among the interrupt request signals 11, iRO has the highest priority, iRl
, iR2 and are assigned successively lower priorities, with iRn having the lowest priority.

At initialization, the value “m” is sent to register 2 from internal bus 3.
” (m≠0) is set, and counter 1 is cleared to zero.

Counter 1 is connected to interrupt request signal line iRn and counts signal pulses input to interrupt request signal line iRn.

The contents of the counter 1 and the register 2 are input to the comparator 4 and compared, and if the contents of the two match, a logic "1" is outputted to the match signal line 5.

Then, when the first iNTA is at logic "0", the data is held in the latch 6, and the control signal line 7 clears the counter 1 to zero, and the control signal line 7' receives an interrupt from iRO to 1R0-1. All outputs of the request register 10 are masked.

Therefore, at that point, iRn has the highest priority and interrupt processing begins.

When the second i RTA is input, the comparator 4 has already detected a mismatch and the logic “0” is sent to the match signal line 5.
is output, the interrupt request mask from iRo to 1Ra-1 is released, and the normal priority order is restored at the end of the iRn interrupt processing routine.

By repeating the above operations, interrupt processing requests are controlled.

FIG. 2 is a block diagram showing a second embodiment of the invention.

Comparator 4. Coincidence signal line 5,1 Transfer controlled by NTA 12. The latch 6 and control signal lines 7, 7 are the same as in the first embodiment.

The interrupt mask register 14 is the one explained in the conventional example.
An interrupt mask register 13 is added, and control information of the interrupt mask register 13.14 is switched by a multiplexer 15 using a control signal line 7.7.

In this embodiment, by adding an interrupt mask register 13, the priority can be freely changed by software.

〔Effect of the invention〕

The interrupt control circuit of the present invention has the advantage that by monitoring the number of pulses of the interrupt request signal, it can automatically process interrupt requests with a low priority, and then return to processing the interrupt requests with a high priority again. There is.

...Interrupt request signal.

Claims (1)

[Claims] A counter that counts interrupt request signal pulses, a register that can be written to from an internal bus, a comparator that compares the contents of the counter and the register and outputs a match signal if they match, and holds the match signal. An interrupt control circuit comprising: a latch for controlling an interrupt;