JPS63280368A - Multi-port memory controller - Google Patents

Abstract

PURPOSE:To reduce a wasteful time due to successive detection by making the diction circuit of memory use request signals into a block so as to decided them and enlarging the number of detectable ports to (n). CONSTITUTION:Memory use request signal selection circuits 14a-14m by blocks which are provided in plural block units of respective ports detect the memory use request signals from respective ports in respective blocks. Gate circuits 15a-15m by blocks are closed for the block of other port in which the memory use request signal is already present until the memory use request signals from all the ports in the same block are processed. The block in which the memory use request signal is absent is passed trough simultaneously with the termination of a block processing in a preceding stage, and a system shifts to the subsequent block in which the memory use request signal is present.

Description

[Detailed description of the invention] [Industrial application field] This invention is a multiport memory controller.

In particular, the present invention relates to a multiport memory controller for shared bus arbitration control in a multi-CPU system that shares memory.

[Prior Art] Figures 3 and 4 show a multi-poling selection method used in line control, etc., as described in, for example, Iwao Hosaka, "Introduction to Data Communication Systems," published by Ohm Publishing, p. 118. FIG. 2 is a configuration diagram of a conventional multi-port memory controller used for port memory arbitration control.

FIG. 3 is a configuration diagram showing an example of the configuration of a multi-CPU system showing the positioning of a multi-port memory controller. In FIG. 0, (1) is a group of CPUs;
I, CPU2. ...-, CPUn. (2
) is a multi-port memory controller whose input and output sides are connected to a CPU group (1) via a memory use request signal line group (5) and a memory use approval signal line 1 (6), respectively. (3) is a common memory.

It is interconnected with the CPU group (1) via a shared bus (4).

FIG. 4 is a block diagram of a multi-port memory controller in the case of 4 ports using the conventional polling method. In FIG. 0, (5a) to (5d) are memory use request signals input from each CPU, (6a) to (6d) is a memory use approval signal to each CPU, (7) is an oscillation circuit that generates basic timing to test whether there is a memory use request from the CPU, and (8) is an oscillation circuit for turning on/off the basic timing signal. It is a gate circuit, and its input side is an oscillation circuit (7
) is connected to the output side of the (9) is a timing generation circuit whose input side is connected to the output side of the gate circuit (8), and the output of the gate circuit (8) causes the CP
Generates timing to sequentially test whether there is a memory use request from U. (10) is a latch circuit, one input side of which is connected to the timing generation circuit (9), and the other input side connected to each line to which memory use request signals (5a) to (5d) are applied. , latches the memory use request status and outputs it to the CPU as a memory use approval signal. (11) is an OR circuit.

Its input side is each line to which memory use approval signals (6a) to (6d) are applied, and its output side is a gate circuit (8),
They are connected to each other, and notify the off-state of basic timing generation to the gate circuit (8) while outputting a memory use approval signal.

A conventional multiport memory controller is configured as described above, and when it becomes necessary to use the common memory (3), a memory use request signal is sent from the CPU to the multiport memory controller (2) through the line (5). A memory use request is made to the

In contrast, the multiport memory controller (2) outputs certain timing signals (21), (22), (23), ( Successive CP with 24>
U + , CPU 2 , . . . are tested for the presence or absence of a memory use request signal, and if the presence of a memory use request signal is detected by the latch circuit (10), then
It immediately outputs the corresponding memory use approval signal (6), and tests the presence or absence of the primary memory use request signal using the OR circuit (11) and gate circuit (8) until the memory use request signal is turned off on the CPU side. Interrupted. When the access is completed on the CPU side and the memory use request signal is turned off, the latch circuit (10) turns off the corresponding memory use approval signal.

The test for the presence or absence of the memory use request signal is restarted through the OR circuit (11), the gate circuit (8), and the timing generation circuit (9).

[Problems to be Solved by the Invention] In the conventional multi-port memory controller device as described above, all memory use request signal groups are sequentially received one by one regardless of the presence or absence of memory use request signals from each CPU. While switching, the presence or absence of a memory use request signal was detected in order.

Furthermore, when the number of memory use request signal groups increases, there is a problem in that too much time is wasted in line priority control.

The present invention was made to solve such problems, and an object of the present invention is to obtain a multi-baud 1-memory controller that can give priority control to all lines equally and at high speed when there are a large number of lines.

[Means for Solving the Problems] A multiport memory controller device according to the present invention includes an oscillation circuit that generates basic timing.

A control gate circuit that drives and stops the output signal of the oscillation circuit, a timing generation circuit that generates a constant timing based on the output signal from the gate circuit, and a block that detects memory use request signals from each port in block units. Successive switching is performed for each block by another memory use request signal selection circuit and the memory use request signal selection circuit for each block.

In order: A latch circuit that outputs a memory use approval signal to the CPU, and a gate circuit for each block that performs switching between blocks in an orderly manner and controls switching of blocks that request memory use to the latch circuit. be.

[Operation] In the present invention, the memory use request signal selection circuit for each block provided in units of multiple blocks of each port detects the memory use request signal from each port for each block, and at the same time, the For ports having a use request signal, a memory use approval signal is issued in order in the block in which the first memory use request signal is detected by the gate circuit and latch circuit for each block, and processing is performed by the CPU. Until the memory use request signals from all ports in the same block have been processed, gate circuits for each block are closed for blocks of other ports that have already received memory use request signals and are waiting for processing of the previous block. And so.

At the same time as the end, blocks with no memory use request signal are passed through and the probe with the primary memory use request signal is passed.

It moves on to ri.

[Embodiment] FIG. 1 is a block diagram showing an embodiment of a multiport memory controller according to the present invention.
, (8) are the same as in FIG. (9a) is a timing generation circuit, (10a) to (10rn) are latch circuits for each block, (lla) to (11m) are OR circuits for each block, and memory use approval signals (6a) to (10rn) are OR circuits for each block.
The basic timing signal is stopped during the output of 6z). (
12) is a general OR circuit which takes the OR of all output signals of the OR circuits (lla) to (l1m) of each block. (
14a) to (14m) are memory use request signal selection circuits for each block, which select circuits for each block when n memory use request signals (5a) to (5z) from the CPU are divided into m blocks of 4 ports each. It is determined whether there is a memory use request even if the memory use request is for one port among the four ports. (14a) is the memory use request signal selection circuit of the first block, (14b) is the memory use request signal selection circuit of the second block, . . . (14m) is the m-th block memory use request signal selection circuit.
This is a block memory use request signal selection circuit. In addition,
Among these m blocks of memory use request signal selection circuits, the one selected is the younger block among (14a) to (14m), and the block proceeds sequentially to the larger one.
a) to (15m) are gate circuits of each block.

This block-specific memory use request signal selection circuit (14a
) to ('14m), only the gate of any one block is opened, and the gate circuit for each block (15a
) to (15m) are sent to the latch circuits (10a) to (10m) corresponding to each block.
) is latched. (17) is a falling edge detection and reset pulse generation circuit, which completes the output of memory use approval signals (6a) to (6z) for each block of memory use request signal selection circuits (14a) to (14m) for each block. is detected, and a reset signal is supplied to the timing generation circuit (9a).

FIG. 2 is a diagram showing the signal states of each part in FIG. 1.

In the multiport memory controller configured as described above, when (31a) is set to the "0" level and memory use request signals are output from two locations (5a) and (5j), first, the first block The selection output signal (32a> of the memory use request signal selection circuit (14a) goes to "1" level, opens the input gate of the gate circuit (15a>) of the first block, and outputs the control signal of the next stage block which is the other output. (31b) becomes "1" level, each output signal from the second block onwards is opened regardless of the memory use request signal, and output signals (32b) to (32m) become "0".
level. Here, the gate circuit of the first block (1
5a), only the gate to which the memory use request signal (5a) is input opens and the output signal (16a) goes to the "1" level, and the gate circuit (8) and the timing generation circuit (9a) of the first block operate. By doing this, the constant timing signal (21) outputs the “1” level, so the first
The output of the latch circuit (10a) of the block is set,
It becomes the “1” level. That is, the memory use approval signal (6a
) becomes "1" level, the output of the OR circuit (lla) of the first block and then the general OR circuit (12) both become "1" level, and the output of the clock signal from the gate circuit (8) becomes "1" level. During this time, the CPU executes processing, and upon completion of the processing, the memory use request signal (5a) becomes "0".
" level, and the gate circuit (15a) of the first block becomes inoperative. At this time, the reset signal of the fall detection and reset pulse generation circuit (17) is input to the timing generation circuit (9a).

Timing output signals (21) to (24) are all cleared. First block memory use request signal selection circuit (1
The control signal (31b) of the next stage block of 4a) changes from the 1" level to the °O" level, but the memory use request signals (5e) to (5h) of the second block do not exist (at the "0°" level). state), the output signal (32b) of the memory use request signal selection circuit (14b) of the second block is at the 0''level;
The output signal (31c) is.

Since the output signal (31b) changes from the "1" level to the "0" level, it becomes the "0" level, and the output signal (32b) of the memory use request signal selection circuit (14c) of the third block
c) becomes the "1" level. Therefore.

The first block shifts to the third block, and the memory use approval signal (6j) is output in the same way as the first block.
Processing of PU3 will be performed.

Note that the timing signal of the timing generation circuit (9a) corresponding to the memory use request signal (5j) is the output signal (22).
). As above.

In this embodiment, four ports are divided into one block, and only blocks with memory use request signals are selected, and blocks without memory use request signals are not processed and are skipped.

Processing operations will be performed on the next block.

In the above embodiment, the block-based memory use request signal selection circuits (14a) to (14m) are divided into four ports, but R2 may be provided for each port.

Further, in the above embodiment, a line control method has been described, but similar effects can be obtained even if the method is used for general interrupt processing, control of input/output devices, etc.

[Effects of the Invention] As explained above, the present invention includes an oscillation circuit that generates basic timing, a control gate circuit that drives and stops the signal of the oscillation circuit, and a constant timing that is generated by the signal from the gate circuit. A timing generation circuit, a memory use request signal selection circuit for each block that detects memory use requests from each port in units of blocks, and a memory use request signal detected by the memory use request signal selection circuit for each block to generate the memory use request signal at the timing. A latch circuit that sequentially switches each block according to a signal from the circuit and outputs a memory use approval signal to the CPU in an orderly manner, and a plotter that switches between each block in an orderly manner and requests memory use to the latch circuit. It is equipped with a block-specific gate I/circuit that performs the detection circuit, and the detection circuit for the memory use request signal is divided into blocks for judgment, and the number of detectable ports can be expanded to n ports, reducing wasted time due to sequential detection. This has the effect of controlling a large number of lines quickly, reliably, and in an orderly manner.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a multiport memory controller in the case of n ports according to an embodiment of the present invention. FIG. 2 is an operation timing signal diagram corresponding to FIG. 1. Figure 3 is a diagram showing an example of a multiprocessor system configuration with a conventional multiport memory controller;
The figure is a configuration diagram of a conventional multiport memory controller. In the figure, (7)... oscillation circuit, (8)... gate circuit, (9a)... timing generation circuit, (10a)...
) ~ (10m)...Latch circuit for each block, (11
a) ~ (11m>... OR circuit for each block, (12
>...Comprehensive OR circuit, (14a) to (14m)...
Memory use request signal selection circuit for each block (15a)
~(15m)...Gate circuit for each block, (17)
... Fall detection and reset pulse generation circuit. In addition, the same reference numerals in each figure indicate the same or corresponding parts. Figure 1, yf) Figure 2, Procedural Amendment Document dated October 14, 1986.

Claims (1)

[Claims] An oscillation circuit that generates basic timing, a control gate circuit that drives and stops the output signal of the oscillation circuit, a timing generation circuit that generates constant timing using the output signal from the gate circuit, and memory usage from each port. A block-by-block memory use request signal selection circuit that detects a request signal in units of blocks, and a latch circuit that sequentially switches each block by the block-by-block memory use request signal selection circuit and outputs the memory use approval signal to the CPU in an orderly manner. and a gate circuit for each block that performs switching between blocks in an orderly manner and controls switching of blocks requesting memory use to the latch circuit.