JPH02110359U - - Google Patents
Info
- Publication number
- JPH02110359U JPH02110359U JP1811489U JP1811489U JPH02110359U JP H02110359 U JPH02110359 U JP H02110359U JP 1811489 U JP1811489 U JP 1811489U JP 1811489 U JP1811489 U JP 1811489U JP H02110359 U JPH02110359 U JP H02110359U
- Authority
- JP
- Japan
- Prior art keywords
- glass substrate
- forming
- circuit pattern
- spin
- semiconductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011521 glass Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims 1
- 230000007261 regionalization Effects 0.000 claims 1
- 230000008961 swelling Effects 0.000 claims 1
- 239000010409 thin film Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Structure Of Printed Boards (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Description
第１図は、この考案の一実施例の要部の断面図
、第２図ａ及び第２図ｂは、それぞれ他の実施例
の平面図及び側面図、第３図は、同実施例のスピ
ンコーターの運転状態を示す図、第４図は、スピ
ンコーターの基本的な構成を示す図、第５図は、
同要部の平面図、第６図は、同スピンコーターの
運転状態を示す図である。
１……スピンコーター、３……ガラス基板、３
ａ……コーナー部、１１……面取部、１３……穴
。
FIG. 1 is a sectional view of a main part of one embodiment of this invention, FIGS. 2a and 2b are a plan view and a side view of another embodiment, respectively, and FIG. FIG. 4 is a diagram showing the operating state of the spin coater, and FIG. 5 is a diagram showing the basic configuration of the spin coater.
FIG. 6, a plan view of the main parts, is a diagram showing the operating state of the spin coater. 1...Spin coater, 3...Glass substrate, 3
a...corner part, 11...chamfered part, 13...hole.
Claims (1)
所定の回路パターンを形成するためのガラス基板
であつて、パターン形成に備えてスピンコートさ
れるフオトレジストの盛り上がりを防止する表面
張力低減部を外周部に設けてなる回路パターン形
成用ガラス基板。 A glass substrate for forming a predetermined circuit pattern on the surface using various conductive, semiconductive, etc. thin films, and a surface tension reducing part that prevents swelling of photoresist that is spin-coated in preparation for pattern formation. A glass substrate for forming a circuit pattern, which is provided on the outer periphery.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1811489U JPH02110359U (en) | 1989-02-18 | 1989-02-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1811489U JPH02110359U (en) | 1989-02-18 | 1989-02-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02110359U true JPH02110359U (en) | 1990-09-04 |
Family
ID=31232466
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1811489U Pending JPH02110359U (en) | 1989-02-18 | 1989-02-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02110359U (en) |
-
1989
- 1989-02-18 JP JP1811489U patent/JPH02110359U/ja active Pending