JPH0211020A - Phase synchronizing circuit - Google Patents

Abstract

PURPOSE:To scarcely cause out of phase by comparing a signal with a signal wide in phase range, when many out of phase occur in accordance with the number of times of out of phase in comparing with a signal having plural different phase ranges, thus selecting a signal. CONSTITUTION:The circuit provides phase difference detecting means 9 and 10 to detect plural phase differences, means 11 and 12 to select and set the phase difference detecting means corresponding to the phase difference detected by the phase difference detecting means 9 and 10 and a means 8 to correct an output phase corresponding to the input phase. The selection is executed so as to compare a signal with a signal having plural different phase ranges and compare the signal with a signal having a wide phase range when the out of phase becomes larger in accordance with the number of times of out of phase. Thus, the phase synchronization error becomes smaller, then the out of phase scarcely occurs.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a phase locked circuit.

[Conventional technology]

An example of a conventional phase locked circuit is shown in FIG. 2 and will be described.

In the figure, 21 is a clock input terminal, 22 is a phase synchronization input terminal, 23 is a phase synchronization output terminal, and 24 is a comparison phase input terminal. 25 is a phase synchronized oscillation circuit, 26 is a counter circuit, and 27 is a gate circuit which receives the signal from the phase synchronization input terminal 22 and the signal from the comparison phase input terminal 24. The output of this gate circuit 27 is a color/color signal. It is configured to be supplied to a reset input of circuit 26.

FIG. 3 is a time chart for explaining the operation of FIGS. 1 and 2, and (凰) indicates the signal PIN.
(b) is signal human power Gz, (e) is signal human power G1, (d)
indicates the signal POUT. And Wl.

W2 indicates time width (phase range).

Next, the operation of the phase locked circuit shown in FIG. 2 will be explained with reference to FIG. 3.

Now, the clock input terminal 21 is connected to the phase synchronization input terminal 22.
A signal PxN (third (
1(a)) is applied, and the counter circuit 26 is reset when the output of the gate circuit 27 is rLJ, and the phase synchronization output terminal 23 receives the signal POυT (third
(see figure (d)). It is also assumed that the clock input C1 applied to the clock input terminal 21 is synchronized with the output clock C2 of the phase synchronized oscillation circuit 25.

At this time, the phase synchronization input terminal 22 receives the signal PIN, and the comparison phase input terminal 24 of the gate circuit 27 outputs rLJ.
When , the counter circuit 26 is reset until the output reaches t of rHJ. When the comparison phase input terminal 24 of the gate circuit 2T is rHJ, the output of the gate circuit 2T becomes rLJ at time t shown in FIG. poo'
r is output. That is, the signal PIN and the signal pot
i comes to operate in synchronization with time tK. here,
Signal input Gl of comparison phase input terminal 24 (Fig. 3(c)
(see) operates in synchronization with the counter circuit 26, and at the same time as the counter circuit 26 is reset, the time width (phase range) Wl becomes rLJ.

Then, the phase synchronization input terminal 22 periodically receives the signal P! Even if the wing is added, the comparison phase input terminal 24 of the gate circuit 27 appears as rLJ, so the counter circuit 26 is not reset. Then, the clock C1 of the phase synchronized oscillation circuit 25 is
When the phase relationship between the output clock C2 and the output clock C2 is shifted and the comparison phase input terminal 24 becomes [HJ], the counter circuit 26 is reset when the signal PIN is applied to the phase synchronization input terminal 22. In this way, the signal PIN and the signal potr'r are phase synchronized.

[Problem to be solved by the invention]

In the conventional phase synchronization circuit described above, if the time width (phase range) Wt in which the signal input G1 applied to the comparison phase input terminal 24 of the gate circuit 2T becomes rLJ is large, an error in the phase synchronization relationship between the signal PIN and the signal POUT occurs. When the time width (phase range) Ws is large and the time width (phase range) Ws is small, the signal PIN and the signal PO
There was a problem that the TJT phase synchronization was easily lost.

[Means to solve the problem]

The phase synchronized circuit of the present invention includes a phase difference detection means for detecting a plurality of phase differences, a means for selecting and setting the phase difference detection means in accordance with the phase difference detected by the phase difference detection means, and a means for selecting and setting the phase difference detection means in accordance with the phase difference detected by the phase difference detection means. It comprises means for correspondingly correcting the output phase.

[Effect]

In the present invention, signals having a plurality of different phase ranges are compared, and depending on the number of times out of phase synchronization, when there are many out of phase synchronization, a signal having a wide phase range is selected for comparison.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing an embodiment of a phase locked circuit according to the present invention.

In the figure, 1 is a clock input terminal, 2 is a phase synchronization input terminal, 3 is a phase synchronization output terminal, 4 is a reset input terminal,
5 and 6 are comparison phase input terminals.

T is a phase synchronized oscillation circuit, and 8 is a counter circuit. Reference numeral 9 denotes a gate circuit which receives the signal from the phase synchronization input terminal 2 and the signal from the comparison phase input terminal 5, and 10 receives the signal from the phase synchronization input terminal 2 and the signal from the comparison phase input terminal 6. These gate circuits constitute phase difference detection means for detecting a plurality of phase differences. 11 is a selector circuit, and 12 is a counter circuit, which constitute means for selecting and setting the phase difference detecting means in response to the phase difference detected by the phase difference detecting means. And counter circuit 8
constitutes means for correcting the output phase in accordance with the input phase.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. 3.

First, each comparison phase input terminal 5, 6 of gate circuit 9, 10
are respectively signal human power G1 + G2 (Fig. 3 (a)
, see (b)) has been added. This signal input G1+G2 operates in synchronization with the counter circuit 8.
When the time tK counter circuit 8 shown in FIG. 3 is reset, the signal input G1. Assume that G2 simultaneously becomes rLJ with time width (phase range) Wl + W2. Further, the counter circuit 12 uses the output of the selector circuit 11 as a clock input, and the counter circuit 12 counts up every time there is an output from the selector circuit 11. The selector circuit 11 selects the terminal Ao according to the count number of the counter circuit 12.
t or terminal A1 is selected, and when the count number is less than or equal to the numerical value M, the terminal Ao is selected, and when the counted number is greater than or equal to the numerical value M, the terminal AI is selected. And counter circuit 1
2 is reset by inputting a reset signal from the reset input terminal 4 every cycle T.

Next, the signal PxN (#$3 figure (
, )) is input, and when the comparison phase input terminals 5 and 6 of the gate circuits 9 and 10 are rHJ, the output of the gate circuit 9 causes the selector circuit 11 to select the terminal AO, so that the counter circuit 12 counts up.

At this time, the counter circuit 8 is reset at the same time, the signal POUT (see FIG. 3(d)) is outputted from the synchronous output terminal 3, and the signal PXN and the signal POtlT are phase synchronized. Also, at the same time as the counter circuit 8 is reset, the comparison phase input terminal 5 becomes "L", and the signal prs is output at the same period.
is added, the signal PrN has a phase range (time width)
Below WI, there is no output from the gate circuit 9, so the counter circuit 12 does not count up.

Next, when the signal pzs exceeds the phase range (time width) W1 and counts M within the υ period T, the counter circuit 8 is reset and at the same time the selector circuit 11 selects the terminal AI. Then, since the phase range (time width) Wl of the comparison phase input terminal 60 of the gate circuit 10 becomes Wl)Wl, if the stability of the phase synchronized oscillation circuit T is the same, terminal A is selected and the running force is out of phase synchronization. and becomes K<.

Then, the selector circuit 11 determines whether the phase synchronization that occurs within the period T is within the υ phase range (
By selecting Wt-* or Wl (time width), the signal PIN and the signal pou'r operate in phase synchronization.

〔Effect of the invention〕

As explained above, the present invention compares signals having a plurality of different phase ranges, and selects signals having a wide phase range when the phase synchronization is large depending on the number of times the phase synchronization is lost. By doing so, there is an effect that the phase synchronization error is small and the phase synchronization can be lost and K<<.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a phase-locked circuit according to the present invention, FIG. 2 is a block diagram showing an example of a conventional phase-locked circuit, and FIG. 3 is an explanation of the operation of FIGS. 1 and 2. This is a time chart for the 7... Phase synchronized oscillation circuit, 8... Counter circuit, 9, 10... Gate circuit, 11... Selector circuit, 12... Counter circuit.

Claims (1)

[Claims] Phase difference detection means for detecting a plurality of phase differences; means for selecting and setting the phase difference detection means in accordance with the phase difference detected by the phase difference detection means; and means for correcting the output phase in accordance with the input phase. A phase synchronized circuit comprising: means.