JPH057895B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a frequency comparison circuit suitable for use in, for example, a pitch controller in speech synthesis, which compares and determines the magnitude of the frequencies of a plurality of pulse signals.

BACKGROUND ART AND PROBLEMS Conventionally, various methods have been proposed for comparing and determining the magnitude of the frequencies of a plurality of pulse signals, and one example is a method using a so-called frequency counter. This method counts and determines the number of pulses of each of the multiple pulse signals to be measured during a certain gate time, and is an extremely traditional method. Therefore, the accuracy can be improved accordingly. However, this method requires a large number of gate circuits, counters, etc., and has drawbacks such as a complicated circuit configuration and high cost.

Another method is to use a so-called frequency-voltage conversion method to perform frequency-voltage conversion on each of the multiple pulse signals to be measured, and then compare the converted voltage values of the two to make a determination. but,
This method has disadvantages such as calibration and accuracy of the frequency-to-voltage conversion and the inability to incorporate it into a pure digital IC.

Furthermore, as another method, digital UP/
Using the DOWN counter, its UP clock terminal,
It is also conceivable to apply a plurality of pulse signals to be measured to the DOWN clock terminal and process the pulse signals based on their UP/DOWN states. However, in this method, the UP clock terminal or
If one of the DOWN clock terminals is in the active state, it is necessary to set a condition to keep the other in the non-active state. Even if a circuit configuration can be devised that makes this condition setting unnecessary. However, the digital UP/DOWN counter itself and its associated peripheral circuits have drawbacks such as complicated circuit configuration and high cost.

OBJECTS OF THE INVENTION In view of the above points, it is an object of the present invention to provide a frequency comparison circuit that has a simple circuit configuration, high accuracy, and can be easily incorporated into a digital IC.

Summary of the Invention The present invention comprises a latch means to which a plurality of pulse signals of different frequencies are supplied, and a comparison means to which an output signal of the latch means and the plurality of pulse signals are supplied, and an output signal of the latch means is provided. The signal is compared with the following plurality of pulse signals delayed from this output signal, and a discrimination signal representing the magnitude of the frequency is generated depending on the degree of coincidence of the logical levels of both signals. This is a frequency comparison circuit. To explain in more detail, for example, as shown in FIG. 3, f ₁ and f ₂ with different frequencies
the first latching means 11, 12, 13 to which two pulse signals are supplied; the two pulse signals and the output signal 3 of the first latching means 11, 12, 13;
Q is supplied and the frequency of the above two pulse signals is
A second circuit that outputs a discrimination signal 6Q representing the magnitude of f ₁ and f ₂
latching means 14, 15, 16, the first latching means 11, 12, 13 has an output signal 3Q.
is [L], one of the above two pulse signals f ₁
It is preset at the rising edge or falling edge of f2, and is cleared at the rising edge or falling edge of the other of the two pulse signals _f2 when the output signal 3Q is [H], and the second latch means 14 , 15, 16 are
When the output signal 6Q is [L] and the output signal 3Q of the first latch means 11, 12, 13 is [H], the pulse signal is preset at the rising edge or falling edge of one of the two pulse signals _f1 . At the same time, when the output signal 6Q is [H] and the output signal 3Q of the first latch means 11, 12, 13 is [L], it is cleared at the rising edge or falling edge of the other of the two pulse signals _f2 . This frequency comparison circuit is characterized by having a simplified configuration compared to conventional circuits, and because the circuit configuration is a pure digital configuration, it can be easily incorporated into a digital IC, and it can perform highly accurate comparison judgments. can.

Embodiments Hereinafter, the present invention will be explained with reference to FIGS. 1 to 4.

Frequency f ₁ , f ₂ of multiple pulse signals, for example, two pulse signals
If we focus on the edge of these pulse signals, for example, the rising edge, we will find the following characteristics.

That is, first, when f ₁ <f ₂ , a pattern as shown in FIG. 1A will always appear, but a pattern as shown in FIG. 1B will never appear. In other words, if a pattern as shown in FIG. 1A appears, it can be seen that the frequencies f ₁ and f ₂ have a relationship of f ₁ <f ₂ .

Conversely, when f ₁ >f ₂ , a pattern as shown in FIG. 1A will never appear, but a pattern as shown in FIG. 1B will definitely appear. In other words, if a pattern like the one shown in Figure 1B appears, the frequencies f ₁ and f ₂
It can be seen that there is a relationship of f ₁ > f ₂ .

Therefore, in this invention, for example, a pattern that always appears depending on the frequency relationship of two pulse signals f ₁ < f ₂ or f ₁ > f ₂ is detected, and whether this detected pattern is in the state shown in FIG. , or the state shown in FIG. 1B, the magnitude of the frequency is determined.

FIG. 2 shows the basic configuration of the present invention. In the figure, 1 and 2 are input terminals to which pulse signals of frequencies f ₁ and f ₂ are supplied, respectively. 2 is connected to the first and second input terminals T ₁ , T ₂ of the latch means 3 and to the first and second input terminals T ₁ , T ₂ of the comparison means 4 . Therefore, the pulse signals from the input terminals 1 and 2 are supplied to the first and second input terminals T ₁ and T ₂ of the latch means 3 and the comparison means 4 at the same timing in terms of timing.

Further, the output side of the latch means 3 is connected to the third input terminal T3 of the comparison means 4, and the output side of the latch means ₃ is connected to the third input terminal T3 of the comparison means 4. , signals of logically different levels are output. For example, when the pulse signal of frequency f ₁ supplied to input terminal 1 is [H], a signal of [H] is obtained at the output side of latch means 3, but the pulse signal of frequency f ₂ supplied to input terminal 2 is When the signal is [H], a [L] signal is obtained at the output side of the latch means 3.

The comparison means 4 compare the output signal from the latching means 3 already applied to the third input terminal T ₃ and the current pulse signal (latching) applied to the first and second input terminals T ₁ and T ₂ respectively. The pulse signals delayed by substantially one clock from the output signal of means 3 are compared, and if they are logically the same, the frequency of the plurality of pulse signals to be measured is f ₁ on the output side. A discrimination signal indicating that there is a relationship of >f ₂ ,
On the other hand, if they are not the same, a determination signal is generated on the output side indicating that there is a relationship of f ₁ <f ₂ .

For example, 1 at the third input terminal T ₃ of the comparison means 4
When the output signal supplied one clock minute ago is [H] and the next pulse signal supplied to the first input terminal _T1 of the comparison means 4 is [H], the output side of the comparison means 4 is outputs a [H] signal indicating that the frequencies of the pulse signals supplied to input terminals 1 and 2 are in the relationship f ₁ > f ₂ , which is sent to output terminal 5 as a discrimination signal. .

Further, the output signal supplied to the third input terminal T ₃ of the comparison means 4 one clock ago was [L], and the pulse signal supplied to the second input terminal T ₂ of the comparison means 4 next was [L]. When the signal is [H], a signal [L] is output to the output side of the comparison means 4, which indicates that the frequencies of the pulse signals supplied to the input terminals 1 and 2 are in the relationship f ₁ < f ₂ . , which is sent to the output terminal 5 as a discrimination signal.

FIG. 3 shows an example of a specific circuit configuration. In the same figure, the latch means 3 includes, for example, D-type flip-flop circuits (hereinafter referred to as F/F circuits) 11 and 12, a preset terminal, and a clear terminal. The input terminals 1 and 2 are connected to the clock terminals of the F/F circuits 11 and 12, respectively. The inverted output terminal 1 of the F.F circuit 11 is connected to the preset terminal 3PR of the latch circuit 13, and the inverted output terminal 2 of the F.F circuit 12 is connected to the clear terminal 3 of the latch circuit 13. In addition, the output terminal 3Q of the latch circuit 13
is connected to the clear terminal 2 of the F/F circuit 12,
The inverting output terminal 3 of the latch circuit 13 is connected to the clear terminal 1 of the F.F circuit 11.

The comparison means 4 includes, for example, F/F circuits 14 and 15.
and a latch circuit 16 having a preset terminal and a clear terminal, and input terminals 1 and 2 are connected to respective clock terminals of F/F circuits 14 and 15, respectively. The inverting output terminal 4 of the F.F circuit 14 is connected to the preset terminal 6 of the latch circuit 16,
The inverting output terminal 5 of the F.F circuit 15 is connected to the clear terminal 6 of the latch circuit 16. Further, the output terminal 6Q of the latch circuit 16 is connected to the clear terminal 5 of the F.F circuit 15, and the inverted output terminal 6 of the latch circuit 16 is connected to the clear terminal 4CL of the F.F circuit 14. Then, the output terminal 5 of the frequency comparison circuit is taken out from the output terminal 6Q of the latch circuit 16.

Next, the operation of the circuit shown in FIG. 3 will be explained with reference to the signal waveforms shown in FIG. 4.

Now, before time _t1 in FIG. 4, it is assumed that, for example, the levels on the output side of the latch circuits 13 and 16 are initialized as shown by broken lines in FIG. 4 E, F and I, J, respectively. Then, latch circuit 1
The F/F circuits 11 and 15 are in a clear state due to the output [L] of the inverting output terminal 3 of No. 3 and the output [L] of the output terminal 6Q of the latch circuit 16, respectively.

Therefore, at time t ₁ , the frequency f ₂ as shown in FIG.
When the pulse signal of is supplied from the input terminal 2 to the F/F circuit 12, the output of the inverting output terminal 2 of the F/F circuit 12 becomes [H] in synchronization with the rising edge as shown in FIG. 4D. As a result, the latch circuit 13 is cleared, and the output terminal 3 of the latch circuit 13 is cleared.
Each output of Q and inverting output terminal 3 is shown in Fig. 4E.
and [L] and [L] from [H] as shown in
It is inverted to [H].

Also, at time t ₁ , the pulse signal of frequency f ₂ is F・F
It is supplied to the circuit 15 and its inverted output terminal 5
The output remains unchanged at [H], and therefore the latch circuit 16 at the next stage also remains in the clear state as shown in FIG. 4F.

Note that the hatched portions in FIGS. 4C, D, G, and H represent that the latch circuits 13 and 16 are held in a preset or clear state and cannot be changed.

Next, at time t ₂ , when a pulse signal with a frequency f ₁ as shown in FIG. Then, in synchronization with the rising edge, the output of the inverting output terminal 1 of the F/F circuit 11 becomes the fourth
As shown in FIG. , it is reversed from [L] to [H] and from [H] to [L], and F・F
The signal is supplied to an input terminal 4D of the circuit 14 and an input terminal 5D of the F/F circuit 15, respectively. At this time, the outputs [H] and [L] of the latch circuit 13 cause the F.F circuits 12 and 11 to be in a non-cleared state and a cleared state, respectively.

In addition, at this time _t2, the frequency is also applied to the F/F circuit 14.
Although the pulse signal of f ₁ is supplied, the input that appears at the input terminal 4D in advance is [L], so
The output of the inverting output terminal 4 remains at [H] as shown in FIG. 4G, and therefore the latch circuit 16 is in a clear state.

Then, at time _t3 , the frequency increases as shown in Figure 4A.
The pulse signal of f ₁ is sent from input terminal 1 to F/F circuit 11
and 14, the outputs of the F.F. circuit 11 and even the latch circuit 13 do not change as shown in FIG. 4C, E, and F, respectively.
4 comes to output the [H] that was applied to the input terminal 4D in synchronization with the rising edge of the supplied pulse signal, and as a result, the output of the inverted output terminal 4 becomes [[H] as shown in FIG. 4G. H] changes to [L],
This presets the latch circuit 16 as shown in FIG. 4G. By presetting this latch circuit 16, the outputs of its output terminal 6 and inverting output terminal 6 are inverted from [L] to [H] and from [H] to [L], as shown in FIG. 4 I and J, respectively. As a result, the F/F circuits 14 and 15 are brought into a clear state and a non-clear state, respectively.

Next, at time t ₄ , as shown in FIG. 4B, the frequency f ₂
When the pulse signal is supplied from the input terminal 2 to the F/F circuits 15 and 12, the F/F circuit 15 changes the input that was previously supplied to the input terminal 5D to [L].
Therefore, at the time this pulse signal is supplied, the output of the inverted output terminal 5 remains [H], and therefore, the outputs of the output terminal 6 and the inverted output terminal 6 of the latch circuit 16 are also as shown in FIG. As shown in I and J, there is no change, and they remain held at [H] and [L], respectively. On the other hand, the F/F circuit 12 synchronizes with the rising edge of the supplied pulse signal and outputs the output from its inverted output terminal 2 as shown in FIG. 4D.
The latch circuit 13, which was in the preset state, is inverted from [H] to [L], and the latch circuit 13, which was in the preset state, becomes the clear state, and the outputs of the output terminal 3 and the inverted output terminal 3 become as shown in FIG. 4, E and F, respectively. As shown in
Invert from [H] to [L] and from [L] to [H].

By inverting each output of this latch circuit 13,
The F/F circuits 12 and 11 are in a clear state and a non-clear state, respectively, and outputs [L] and [H] are supplied to the input terminal 4D of the F/F circuit 14 and the input terminal 5D of the F/F circuit 15, respectively. be done.

Furthermore, at time _t5, as shown in FIG. 4A, the frequency _f1
When the pulse signal is supplied to the F/F circuits 14 and 11 from the input terminal 1, the F/F circuit 14 receives this pulse signal because the input supplied to its clear terminal 4 in advance is [L]. At the time when is supplied, the output of the inverting output terminal 4 remains [H], and therefore the outputs of the output terminal 6Q and the inverting output terminal 6 of the latch circuit 16 also become as shown in FIG. 4 I and J, respectively. They remain unchanged at [H] and [L], respectively. On the other hand, the F/F circuit 11 synchronizes with the rising edge of the supplied pulse signal.
The output of the inverting output terminal 1 of the F circuit 11 changes from [H] to [L] as shown in FIG. 4C, whereby the latch circuit 13 is brought into the preset state again. As a result, the respective outputs of the output terminal 3Q and the inverted output terminal 3 of the latch circuit 13 are
As shown in Figures E and F, the input terminal 4D of the F/F circuit 14 and the input terminal 5D of the F/F circuit 15 are inverted from [L] to [H] and from [H] to [L].
are supplied respectively. Also, at this time, the latch circuit 13
The F.F circuits 12 and 11 are brought into a non-clear state and a clear state by the outputs [H] and [L], respectively.

Then, even if a pulse signal of frequency f ₂ is supplied from input terminal 2 to F/F circuits 15 and 12 at time t ₆ , the same operation as at time t ₄ described above is repeated, and each output of latch circuit 16 changes. There isn't. Similarly, there is no change in each output of the latch circuit 16 at each time point after time _t6 . That is, after time _t3 , the output of the output terminal 6Q of the latch circuit 16 is always held at [H].

Therefore, when a plurality of pulse signals of the pattern shown in FIG. 4A and B (that is, the pattern corresponding to FIG. 1B) are supplied, the output terminal 5
A determination signal of [H] indicating that the frequency relationship between both pulse outputs is f ₁ >f ₂ is sent out.

Furthermore, if the frequency relationship of the plurality of pulse signals to be measured is f ₁ < f ₂ , that is, if a signal with a pattern equivalent to Fig. 1A is supplied, as a result, although the explanation of its operation is omitted, this In this case, an [L] determination signal is sent to the output terminal 5.

Note that if the frequency relationship of a plurality of pulse signals to be measured is f ₁ =f ₂ , the circuit operation becomes undefined.

In this way, in this embodiment, the two pulse signals to be measured are supplied to the input terminals 1 and 2, respectively, and the logic processing is performed, and the output signal of the output terminal 5 is easily monitored by simply checking the logical level of the output signal. It is possible to determine the magnitude of the frequency of two pulse signals.

Note that the circuit example in Figure 3 is just an example, and other circuit configurations may be used as long as the same function can be achieved.
Also, instead of latch circuits 13 and 16, J-K
A type F/F circuit or a D type F/F circuit may be used.

In addition, the frequency of the multiple pulse signals to be measured may be so high that the circuit cannot follow them, or the frequencies may be very close to each other and the edge time difference between each pulse signal may be too short, causing the circuit to fail. If malfunction is likely to occur due to internal delay time, for example, a prescaler may be provided at the stage before input terminals 1 and 2 to divide the frequency of the input pulse signal.

In addition, in the above embodiment, there are two pulse signals, but the same can be done in the case of a larger number of pulse signals. Or, for example, if we consider frequencies f ₁ , f ₂ , f ₃ , we can prepare a circuit like the one shown in Figure 3 for each pair of frequencies and output the results in a time-sharing manner, for example. You can do it like this.

Effects of the Invention As described above, according to the present invention, a circuit configuration is provided that focuses on a pattern that always appears and a pattern that never appears of frequencies having a certain magnitude relationship, and determines the magnitude of the frequency by detecting the pattern that always appears. Therefore, the scale is smaller and the configuration is simpler than the conventional circuit, and since the circuit configuration is a pure digital configuration, it can be easily incorporated into a digital IC.

In addition, since only the edge of the pulse output to be measured is used, it is independent of the pulse width and is unaffected by fluctuations in the duty ratio, making it possible to perform highly accurate comparative judgments. Become.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining this invention;
FIG. 2 is a block diagram showing the basic configuration of this invention.
FIG. 3 is a circuit configuration diagram showing an embodiment of the present invention;
FIG. 4 is a diagram for explaining the operation of FIG. 3. 3 is a latch means, 4 is a comparison means, 11, 12,
14, 15 are D-type flip-flop circuits; 13,
16 is a latch circuit.

Claims (1)

[Claims] 1. A first latch means to which two pulse signals of different frequencies are supplied; and a first latch means to which the two pulse signals and the output signal of the first latch means are supplied; It has a second latch means that outputs a discrimination signal representing the magnitude of the frequency, and the first latch means detects the rising edge or the falling edge of one of the two pulse signals when its output signal is [L]. The second latch means is set at the rising edge or falling edge of the other of the two pulse signals when its output signal is [H], and the second latch means is set when its output signal is [L]. When the output signal of the first latch means is [H], it is set at the rising edge or the falling edge of one of the two pulse signals, and when the output signal is [H], the first latch means is set. A frequency comparison circuit characterized in that when the output signal of the means is [L], the frequency comparison circuit is reset at the rising edge or falling edge of the other of the two pulse signals.