JPH04244971A - Pulse interval measuring circuit - Google Patents

Abstract

PURPOSE:To achieve higher measuring resolutions by adding a delay time corre sponding to a changing point of a logic output value of an adjacent phase memory circuit to the count valve of a counter to obtain a measured value. CONSTITUTION:Signal such as start pulse enable from a timing controller 1 is outputted through an OR gate 22 and reset to phase memory circuits 6, 8, 10 and 12 to enable a counter 4. When a start pulse P0 is applied from an input terminal of pulses to be measured, the counter 4 starts an incremental counting. Then, when a first pulse P1 is applied to the input terminal of the pulses to be measured, an AND gate 61 outputs the pulse P1 as intact and a delay output is produced sequentially from other AND gates through a delay element separately to be latched with a D-F/F. An adder 19 adds output values of a register 13 and a fixed value generator 18 and a strobe generator 20 generates a strobe signal and a register 21 outputs an output value of the adder 19 at (m+2) bits.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a circuit that measures the interval on the time axis between two pulses. , relates to a pulse interval measuring circuit in a reciprocating path system that can determine the interval between both pulses.

0002

2. Description of the Related Art Conventionally, environmental resistance and high reliability are considered important in pulse interval measuring circuits such as on-board distance measuring devices used in the aerospace field, which have restrictions on the number of parts that can be used.

FIGS. 3 and 4 are diagrams showing a circuit diagram of a conventional pulse interval measuring circuit and a time chart for explaining its operation, respectively. The conventional example shown in FIGS. 3 and 4 includes a timing controller 1, a counter 4, a register 13, an AND gate 3, and a NAND gate.
D) 61 and an inverter 2.

[0004] The timing controller 1 has a clock (
CK) and an enable signal (ENB) to the counter 4. In addition, the start pulse enable and reset signal (RST) are connected to the input terminal of AND gate 2, register 1.
At the same time, this start pulse enable and reset signal (RST) is output to N through inverter 2.
It is output to one end of the AND gate 61'.

[0005] The NAND gate 61' performs the NAND operation of the pulse to be measured and the signal from the inverter 2, and outputs a strobe signal (STB) to the register 13. Further, the AND gate 3 performs a logical product between the pulse to be measured and the start pulse enable and reset (RST), and outputs a reset signal to the counter 4.

The counter 4 receives a clock (0) and an enable signal (ENB) and outputs an m-bit count value signal to the register 13. Register 13 is RST
It receives the signal, STB signal, and count value signal and outputs an m-bit measured value.

The operation of the conventional pulse interval measuring circuit having such a configuration will be explained. First, the register 13 is reset by a start pulse enable signal from the timing co-controller 1, and the counter 4 is put into operation by an enable (ENB) signal from the timing controller 1. Next, when a start pulse P0 is applied from the pulse input terminal under test and a reset (RST) signal is applied from the timing controller 1 via the AND gate 3, the counter 4 is reset. In this state, the counter 4 starts counting up from 0 according to the clock (CK).

Next, the first pulse (pulse P1) from the start pulse P0 at the pulse input terminal to be measured
, the strobe (ST
B) Since the signal is given to register 13, counter 4
The count value (Nk) at that time is set in the register 13. The counter 4 and the register 13 are composed of m bits, so that the pulse interval is measured with m-bit accuracy using the period T of the clock CK as a time base.

[0009]

The conventional pulse interval measuring circuit shown in FIGS. 3 and 4 uses a value counted using the period T of the clock CK of the pulse interval measuring counter as a time base as the measured value. Therefore, there was a problem that the resolution of the measured value could not be improved beyond the period T of the clock CK.

SUMMARY OF THE INVENTION Therefore, a technical object of the present invention is to provide a pulse interval measuring circuit in which the resolution is improved more than the period T of the clock CK of the pulse interval measuring counter.

[0011]

[Means for Solving the Problems] According to the present invention, in a pulse interval measurement circuit, a counter is started at the interval of a pulse train to be measured, the count is counted by a clock, and the counted value is latched in a first register. , a delay element that sequentially delays the clock by an equal delay increment to obtain a plurality of delayed pulses under test; Detecting a change point in the logical output value between a phase memory circuit that detects the phase between the pulse to be measured and two phase memory circuits in which the phase difference of the measured pulse to be detected is close among the phase memory circuits. an E-OR gate, a fixed value generator that generates a delay time corresponding to the detected change point, an adder that adds the delay time to the count value from the first register, and the delayed measured value. Pulse interval measurement characterized by comprising a strobe generator that is activated by the most delayed of the pulses and generates a strobe signal, and a second register that latches the added value from the adder using the strobe signal. A circuit is obtained.

0012

In the pulse interval measuring circuit of the present invention, the pulse to be measured is sequentially delayed by delay elements having a delay increment T/n, which is obtained by equally dividing the clock CK of period T used by the counter by the number n of phase memory circuits. The phase of the output from this delay element and the output synchronized with the clock of period T is detected by a phase memory circuit, and the change point of the logical output value of two phase memory circuits whose detected phases are adjacent is detected by an E-OR gate. To detect. A delay time corresponding to this change point is generated by a fixed value generator, and added to the count value of the counter 4 by an adder. The strobe generator 20 is activated by the pulse to be measured that delays this addition value the most to generate a strobe signal, and the register 21 is latched. As a result, the measurement resolution of the pulse interval can be increased by the delay increment T/n.

[0013]

[Examples] Examples of the present invention will be described below. FIG. 1 is a circuit diagram showing an embodiment of the pulse interval measuring circuit of the present invention. FIG. 2 is a time chart showing the operation of the pulse interval measuring circuit shown in FIG. In the circuit of Figure 1, Figure 3
Equivalent parts to those in the circuit are shown with the same reference numerals.

In this example, the pulse interval measuring circuit is
Timing controller 1, inverter 2, and (A
ND) Gate 3, counter 4, initial value generation circuit 5, phase memory circuit 6, 8, 10, 12, delay element 7, 9, 11
, registers 13, 21, exclusive OR gate (E-OR
Gate) 14, 15, 16, Noah (NOR)
It includes a gate 17, a fixed value generator 18, an adder 19, and a strobe generator 20.

The phase memory circuits 6, 8, 10, and 12 are provided corresponding to the clock (CK) of the timing controller 1 and the delay pulses of the delay elements 7, 9, and 11, respectively. These phase memory circuits 6, 8, 10, 12 are AND
AND gates 61, 81, 101, 121 for arithmetic processing
and RS flip-flop circuit (RS-F/F) 62,
82, 102, 122, and a D flip-flop circuit (D
-F/F) 63, 83, 103, and 123, respectively.

The timing controller 1 outputs a clock pulse (CK), an enable (ENB) signal, and a start pulse enable, preset (PRST) and reset (RST) signal. This CK is applied to the counter 4 and the respective D-F/Fs 63, 83, 103, 12.
Sent to 3. Further, the ENB signal is input to the counter 4.

Furthermore, the start pulse enable, preset (PRST) and reset (RST) signals are OR
The register 13 and each RS-F/
F62, 82, 102, 122, and D-F/F63,
83, 103, 123, and is input to AND gates 61, 81, 101, 12 via inverter 2.
Enter 1.

The pulse to be measured is directly applied to the AND gate 61 of the phase memory circuit 6 from the pulse to be measured input terminal, and is also input to the delay elements 7, 9, 11, and is further input to the AND gate 61 of the phase memory circuit 6.
The signal is inputted to the counter 4 via the D gate 3 as a PRST signal. The delay elements 7, 9, and 11 are T/4, which is obtained by dividing the period T of the clock (CK) of the timing controller 1 into four equal parts.
The pulse to be measured is delayed with a delay increment of , and the AND gates 81,
101, 121. For this reason, delay elements 7 and 9
, 11 have delay times of T/4, 2T/4, and 3T/4, respectively.

E-OR gate 14 performs exclusive arithmetic processing on the output signals from phase memory circuit 6 and phase memory circuit 8, and outputs the arithmetic results to NOR gate 17 and fixed generator 18. Furthermore, the E-OR gate 15 is connected to the phase memory circuit 8.
Exclusively performs arithmetic processing on the output signals from the
Output to. Similarly, the E-0R gate 16 performs exclusive arithmetic processing on the output signals from the phase memory circuit 15 and the phase memory circuit 16, and outputs the arithmetic results to the NOR gate 17 and fixed generator 18. The calculation result of NOR gate 17 is also output to fixed generator 18 .

[0020] When there is an output from the corresponding E-OR gate 14, 15, 16, the fixed generator 18 represents the fixed values of 3/4, 2/4, and 1/4, respectively, in binary 2 bits. , and if there is no output, 3-input NOR
The fixed value of 1 is represented by two binary bits by the gate 17 and outputted to the adder 19. For this reason, the fixed generator 18 is provided with fixed generation circuits that generate fixed values 3/4, 2/4, 1/4, and 1, respectively.

The adder 19 adds the output value from the register 13 and the 2-bit output value from the eigenvalue generator 18 to obtain m+
A 2-bit signal is generated and input to the register 21. The strobe generator 20 outputs a strobe (STB) signal to the register 21 in response to the output pulse signal from the AND gate 121.

The register 21 latches the output value from the adder 19 upon receiving the strobe (STB) signal, and
Outputs the measured output value in 2 bits.

Next, the operation of the pulse interval measuring circuit according to the embodiment of the present invention will be explained. First, the start pulse enable, preset signal (PRST) and reset (RST) signals from timing controller 1 are turned OFF.
RS-F/F 62, 82 in each phase memory circuit 6, 8, 10, 12
, 102, 122 and D-F/F63, 83, 103
, 123 are reset, and the binary counter 4 is brought into operation by an enable (ENB) signal given from the timing controller 1.

Next, when the first pulse, the start pulse P0, is applied from the pulse input terminal under test, the AN
By receiving the preset (PRST) signal through the D gate 3, the counter 4 receives the - from the initial value generation circuit 5.
1 and starts counting up from -1 using the clock (CK) from the timing controller 1. In this case, the start pulse enable, preset (PRST) and reset (RST) signals close the AND gates 61, 81, 101, 121, so the start pulse P0 is applied to the RS-F/F 62.
, 82, 102, 122.

Next, when the first pulse (pulse P1) from the start pulse P0 is applied to the pulse input terminal to be measured, the AND gate 61 outputs P1 as is, and the AND gates 81, 101, and 121 output the pulse P1 as is. are delay elements (T/4) 7, (2T/4) 9, (3T/
4) RS-F/F62, 8 sequentially delayed output via 11
2, 102, 122, and these RS-F/F
62, 82, 102, and 122 are set. Next, R
The outputs of F-F/F62, 82, 102, and 122 are output to the corresponding D-F/F63 and F-F/F63 at the timing of the clock (CK).
83, 103, and 123. Counter 4 and register 13 consist of m bits, AND gate 1
The count value of the counter 4 when the output pulse is applied from the counter 21 is latched in the register 13.

In FIG. 2, a case is illustrated in which the timing pulse P1 is generated at Nk +5/8, where the true count value is Nk. In this example, AND
The output of the gate 61 is generated when the count value of the counter 4 reaches Nk-1. AND gate 81, 101, 12
The output of 1 is 1/1 from the output of AND gate 61, respectively.
Since it occurs with a delay of 4, 2/4, 3/4, register 13
The count value of is Nk.

In an embodiment of the invention, pulse P1
The timing is measured with a resolution of 1/4 of the LSB of m bits, that is, m+2 bits, and the arithmetic processing at that time is performed as follows. Logic output of D-F/F63, 83 is 1
Since the logic outputs of D-F/Fs 103 and 123 are 0, only E-OR gate 15 generates a logic output of 1 among E-OR gates 14, 15, and 16. . In this way, either one of the E-OR gates 14, 15, and 16 generates an output, or it does not generate an output depending on the timing of the pulse P1.

Fixed value generator 18 includes E-OR gate 14
, 15, and 16, the corresponding fixed values of 3/4, 2/4, and 1/4 are sent out as binary 2-bit outputs, and each E-OR gate 14,
If there is no output from 15 and 16, 3 input NO
The R gate 17 outputs a fixed value of 1 expressed as two binary bits.

Accordingly, in the embodiment of the invention shown in FIG. 2, fixed value generator 18 outputs a binary 2-bit value representing 2/4. The adder 19 adds the output value of the register 13 and the output value of the eigenvalue generator 18 and outputs the addition result. The strobe generator 20 generates a strobe (STB) according to the output pulse signal of the AND gate 121.
A signal is generated, and the register 21 latches the output value of the adder 19 upon receiving this signal and outputs it as m+2 bits.

When the STB signal is generated, the register 13 and phase memory circuits 6, 8, 10, and 12 are reset. The output value of the register 13 is a binary value Nk, and the output value of the fixed value generator 18 is a binary 2-bit value of 2/4, so the output of the register 21 is 1/4 corresponding to (Nk+2/4). It is a binary m+2 bit value with LSB as LSB.

[0031]

[Effects of the Invention] As explained above, in the present invention, the phase of the pulse to be measured following the start pulse is detected by the corresponding phase memory circuit using sequentially delayed signals, and at the same time, the phase of the pulse to be measured following the start pulse is detected by the corresponding phase memory circuit. Since the count value is latched and the delay time corresponding to the change point of the logical output value of the adjacent phase memory circuit is added to the count value of the counter to obtain the measured value, the clock period T of the measurement counter is Delay increment T/n equally divided by the number of memory circuits n
Since pulse intervals can be measured with a resolution of However, it has the effect of dramatically improving measurement resolution.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a pulse interval measuring circuit of the present invention.

FIG. 2 is a diagram showing the operation of the circuit in FIG. 1;

FIG. 3 is a diagram showing the configuration of a conventional pulse interval measuring circuit.

FIG. 4 is a timing chart showing the operation of the circuit in FIG. 3;

[Explanation of symbols]

1 Timing controller 2 Inverter 3 AND gate 4 Binary counter 5 Initial value generation circuit 6 Phase memory circuit 8 Phase memory circuit 7 Delay element 9 Delay element 10 Phase memory circuit 11 Delay element 12 Phase memory circuit 13 First register 14 E-OR gate 15 E-OR gate 16 E-OR gate 17 3 input NOR gate 18 Fixed value generator 19 Adder 20 Strobe generator 21 Second register 22 OR gate 61 AND gate 61´ NAND gate 62 RS-F/F 63　D-F/F 81 AND gate 82 RS-F/F 83　D-F/F 101 AND gate 102 RS-F/F 103　D-F/F 121 AND gate 122 RS-F/F 123　D-F/F

Claims (1)

[Claims] Claim 1: In a pulse interval measurement circuit that starts a counter based on the interval of a pulse train to be measured, counts using a clock, and latches the counted value in a first register, the pulse interval measuring circuit starts a counter based on the interval of the pulse train to be measured, and the counted value is latched in a first register. a delay element that sequentially delays a plurality of delayed pulses under test, and detects the phase between the pulse under test that is synchronized with the clock and the pulse under test that is sequentially delayed by a delay increment from the clock of the delay element. Detecting a change point in the logical output value between two phase memory circuits in which the phase difference of the measured pulse to be detected is close to each other among the phase memory circuits.
- an OR gate, a fixed value generator that generates a delay time corresponding to the detected change point, an adder that adds the delay time to the count value from the first register, and the delayed pulse to be measured; A pulse interval measuring circuit characterized in that it has a strobe generator that is activated by the most delayed one of the strobe signals and generates a strobe signal, and a second register that latches the added value from the adder using the strobe signal. .