JPH0260229A - Phase synchronizing circuit - Google Patents

Abstract

PURPOSE:To reduce a phase difference and to prevent the step out of a phase synchronizing relation by comparing a signal with a signal having different phase range more than two phases for phase synchronization control and after being compared with a signal having the small phase difference, selecting it so as to be compared with the signal having the large phase difference. CONSTITUTION:A signal PIN supplied to a synchronizing input terminal 19 is initially in an L level. When a signal 22 is in an H level, a signal 17 outputted from a NAND gate 16 is in the H level, and a counter circuit 15 is prevented from resetting. Since PIN is in the L level at a time (t), the signal 17 is changed to the L level at that time when PIN changes to the H level, and the counter circuit 15 is reset, whereby a signal POUT is outputted. On the other hand, a switch circuit 36 is switched to the side of a contact point B when the counter circuit 15 is reset. Both signals 22 and 35 are operated synchronously with the counter circuit 15. Since a time w2 when the signal 35 goes to the L level has much time compared to a time w1 even if the phase relation of a clock signal 13 and an output clock 14 is shifted and it is shifted from a timing when the signal 22 goes to the L level, step-out of synchronization is prevented from occurring when shift is within the range of w2.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a phase locked circuit.

[Conventional technology]

FIG. 3 shows an example of a conventional phase locked circuit. This phase-locked circuit includes a phase-locked oscillation circuit 11. Phase synchronized oscillation circuit IH This is input clock terminal 1
A clock signal 13 is supplied from 2, and an output clock 14 synchronized with this is generated. This output clock 14 is supplied to a clock input terminal CIH of a counter circuit 15 and counted.

This counter circuit 15 has its reset input terminal RI N
A signal 17 is supplied from the Nantes gate 16 to the gate. The signal 17 is a signal created by logically calculating the signal pH1 supplied to the synchronization input terminal 19 and the signal 22 supplied to the input terminal 21 using the Nant gate 16. When the signal 17 becomes L level, the counter circuit 1
5 is reset and the signal P is output from its output. U7 is output and supplied to the output terminal 23.

FIG. 4 is for explaining the operation of this phase locked circuit. As shown in FIG. 1A, the signal Pill supplied to the synchronization input terminal 19 is initially at L (low) level, and as shown in FIG.
(high) level.

Therefore, at this point, the signal 17 output from the Nant gate 16 is at H level. In this state, counter 1
5 is not reset. Now, suppose that the signal PIN changes from the L level to the H level at a later time t, as shown in FIG. At this point, the signal 17 changes to L level, and the counter circuit 15 is reset. Along with this,
The signal P as shown in FIG. U, is output. That is, the signal Pi11 and the signal P OUT operate in synchronization with time t.

By the way, in this phase locked circuit, the signal 22 operates in synchronization with the counter circuit 15. That is, at the same time that the counter circuit 15 is reset, the signal 22 is
1 (FIG. 4b).

Therefore, when the signal P is applied periodically from the synchronization input terminal 19, the signal 22 becomes L level in conjunction with the counting result of the counter circuit 15, so the counter circuit 15 itself is not reset. If the phase relationship between the clock signal 13 and the output clock 14 deviates, and as a result, the timing at which the signal 22 reaches the L level deviates, the signal 22
When signal P0 is applied when P0 is at H level, signal 17 changes to L level again and counter circuit 15 is reset.
will be played. In this way, the signal pHl and the signal pout
will be phase synchronized.

[Problem to be solved by the invention]

In the conventional phase-locked circuit described above, when the time width of time W1 shown in FIG. 4 is increased, the signal PIN and the signal P. The error in the phase synchronization relationship of the UT increases. Therefore,
When the time width of time W1 is set small, the signal PI
N and signal P. There is a problem that the phase synchronization relationship between LI and I is likely to deviate.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a phase synchronization circuit that can maintain a phase synchronization relationship even if the time width of time W1 is set small.

[Means to solve the problem]

The present invention includes (i) a phase comparison signal generating means that generates a plurality of phase comparison signals each having a different time width each time a clock signal is input and a predetermined count value is counted; and (ii) (iii) a reset means for resetting the count value when a periodic input signal is supplied at a time when one selected signal among these phase comparison signals is not generated; When the reset operation of the reset means is performed, a switch means for selecting another phase comparison signal having a longer time width than the selected one signal and performing a phase comparison with the input signal; and a phase synchronization circuit. be equipped.

As described above, in the present invention, it is determined whether or not the signal is out of phase with a signal having a longer time width by the selection operation of the switch means, thereby stably maintaining the phase synchronization relationship.

〔Example〕

FIG. 1 shows the phase locked circuit of this embodiment. Components that are the same as those in FIG. 3 are designated by the same reference numerals, and their description will be omitted as appropriate.

Now, in the phase synchronized circuit of this embodiment, the synchronization input terminal 1
The signal PIN input from 9 is supplied to one input terminal of each of the first and second Nant gates 16.32. The other input terminal 21 of the first Nantes gate 16 is supplied with the signal 22 shown in FIG. 3, and the other input terminal 34 of the second Nantes gate 32 is supplied with another signal 35. It has become. The signal 22 and the signal 35 are output according to the count value of the counter circuit 15.
This is a signal that is output, and the signal 22 is L during the time width W1.
In contrast, the signal 35 remains at L level for a longer time width W2.

A switch circuit 36 is arranged on the output side of the two Nant gates 16 and 32, and when its contact selects contact A, the output of the first Nant gate 16 is connected to the reset input terminal RII+ of the counter circuit 15. connected to contact B
When selected, the output of the second Nant gate 32 is connected to the set input terminal RIM of the counter circuit 15. The switch circuit 36 selects the contact point A until the counter circuit 15 is reset for the first time. Then, after being reset by − degrees, contact B is selected thereafter.

The operation of the phase synchronized circuit configured as above will be explained with reference to FIG. 2.

Signal PIN supplied to synchronous input terminal 19 (a in the same figure)
is initially at L level, and as shown in C in the same figure, input terminal 2
Assume that the signal 22 supplied to the circuit 1 is at H level. In this case, the signal 17 output from the first Nant gate 16
is at H level, and the switch circuit 36 connected to the contact is supplied with an H level signal, and the counter circuit 15 is not reset in this state.

Now, at time t later than this, the signal P
Assume that IN changes from L level to H level. At this point, the signal 17 changes to L level, and the counter circuit 15 is reset. At the same time, a signal P is generated as shown in d of the same figure. uT is output. That is, signal PIN and signal P
. 0. starts to operate in synchronization with time t. Furthermore, when the counter circuit 15 is reset, the switch circuit 36 switches its contact to the contact B side.

By the way, both signals 22 and 35 operate in synchronization with the counter circuit 15 in this phase synchronized circuit.

Therefore, when the signal PIN is periodically applied from the synchronization input terminal 19', the signal 35 goes low as shown in FIG.
Since the counter circuit 15 is at the level, the counter circuit 15 itself is not reset. Even if the phase relationship between the clock signal 13 and the output clock 14 deviates, and there is a slight deviation from the timing at which the signal 22 becomes L level, the time W at which the signal 35 becomes L level
2 has more margin than time W1, so this time W2
If the deviation is within the range of , no synchronization will occur.

In the embodiment described above, it was decided to reduce the phase synchronization error and prevent out of phase synchronization by comparing signals with two different phase ranges, but compared with signals having three or more different phase ranges. It is also possible to perform control by

〔Effect of the invention〕

As described above, according to the present invention, signals having two or more different phase ranges are compared for phase synchronization control, and after comparing with a signal with a small phase difference, a signal with a large phase difference is selected for comparison. Therefore, in addition to reducing the phase error,
This has the effect of making it difficult to lose the phase synchronization relationship.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a phase-locked circuit according to an embodiment of the present invention, FIG. 2 is a timing diagram for explaining the operation of this circuit, and FIG. 3 is a circuit diagram of a conventionally used phase-locked circuit.
FIG. 4 is a timing diagram for explaining the operation of this conventional circuit. 11... Phase synchronized oscillation circuit, 15... Counter circuit, 16... First Nantes gate, 32...
- Second Nant gate, 36... switch circuit, PIN... signal, pout... signal, w l , W 2... time width. Applicant: NEC Corporation Representative

Claims (1)

[Scope of Claims] Phase comparison signal generation means for generating phase comparison signals of multiple systems each having a different time width each time a clock signal is input and a predetermined count value is counted; A reset means for resetting the count value when a periodic input signal is supplied at a time when one selected signal among the signals is not generated, and a reset operation of the reset means is performed. and switch means for selecting another phase comparison signal having a longer time width than the selected one signal to perform phase comparison with the input signal.