JPS62104336A - Automatic phase adjusting device - Google Patents

Abstract

PURPOSE:To reduce errors in data discrimination by adjusting and controlling the phases of a data signal and a clock signal automatically all the time based on an error result after the data discrimination. CONSTITUTION:For example, delayed clock signals 213A-213C lead the data signal relatively for some reason and have the time relation shown in figure (c). In this case, the discriminated data state of the 3rd flip-flop 215C is proper, but the discriminated data states of the 1st and the 2nd flip-flops 215A and 215B are improper, so minimum error information appears in the 3rd error signal 219C. Three error signals 219A-219C are converted by a control circuit 221 into voltages and the quantities of delay of the delayed clock signals 213A-213C are increased with a control signal 223 as the voltage signal. This control circuit 221 functions to generate the voltage of the control signal 223 in such a direction that the error of the 2nd error signal 219B is minimized.

Description

[Detailed Description of the Invention] [Summary] An automatic phase adjustment device that identifies the relative timing relationship between data and a clock using a plurality of clock signals with different timings, and calculates the error rate of the phase difference. It was configured to be used for adjustment control.

[Industrial application field]

The present invention relates to an automatic phase adjustment device, and more particularly to an automatic phase adjustment device that uses data identification error rate for phase adjustment.

In fields such as data communications, there is a need to regenerate data and clock signals.

[Conventional technology]

To meet this need, there has been a conventional signal extraction device as shown in FIG. Here, a clock signal component is extracted by a tank circuit 415 from an input signal 413 applied to an input terminal 411, and amplified by an amplifier 417 to obtain a clock signal 419. This clock signal 41
9 is delayed by the delay circuit 421, and the delayed clock signal 4
23 is supplied to a clock input terminal C of a D flip-flop forming a data identification circuit 425. In addition, the input signal 41 is connected to the data input terminal of this flip-flop.
3 is supplied.

The delay circuit 421 matches the relative timing (phase) of the input signal 413 supplied to the data identification circuit 425 and the clock signal 423.

In other words, as shown in FIG. 5, the pulse rising point of the clock signal 423 is the input signal 413 (representing data).
The data is identified approximately at the center of the rising edge.

Therefore, a data output signal 427 representing 1 if the input data is "1" and "0" if the input data is 'O' at the rising edge of the clock signal 423 is output as the Q output signal of the flip-flop.

Further, the data output signal 427 and the clock signal 423 are supplied to an error detector 429, so that an error signal 431 is obtained.

[Problem that the invention seeks to solve]

However, in such a conventional example, even if the delay time by the delay circuit 421 is adjusted to be optimal, it is fixed. However, the tank circuit 415
The rising point of the clock signal 423 is deviated in time due to fluctuations in temperature and humidity, power fluctuations in the delay circuit 421 itself, and the like. Therefore, there was a problem in that the error rate due to the phase shift ended up increasing.

The present invention was created in view of these points,
It is an object of the present invention to provide an automatic phase adjustment device that contributes to improving the error rate by using the error rate to adjust the phase shift.

[Means for solving problems]

FIG. 1 is a block diagram of the principle of the present invention.

In the figure, the clock extraction circuit 115 has an input signal 11
A clock signal 113 is taken out from 1 and output.

The phase adjustment means 123 outputs at least two clock signals 119 and 121 in a predetermined timing relationship in response to the clock signal 113, and outputs at least two clock signals 119 and 121, which are input signals of these clock signals, and a signal used as a data processing clock signal. Adjust the phase relative to the input signal.

Identification circuits 127.131 output clock output signals 119.131.
121, the data state of the data signal 117 is identified and identification signals 125 and 129 are generated.

The control means 135 generates a control signal 133 based on the identification signals 125 and 129 and supplies it to the phase adjustment means 123.

Therefore, as a whole, the input signal 11 is determined according to the identification result.
1 and the clock signal 119 or 121 are aligned in phase.

[Effect]

In the present invention, a clock extraction circuit 115 generates a clock signal 113 in response to an input signal 111 having data and a clock.

A data signal 117 and a plurality of clock output signals 119, 121 are outputted by the phase adjusting means 123 which receives the input signal 111 and the clock signal 113.

A plurality of identification signals 125 and 129 identifying the data state of the data signal 117 are output at timings corresponding to the plurality of clock output signals 119 and 121.

Control signals 133 generated in response to these identification signals 125 and 129 appropriately adjust and control the relative phase relationship between input signal 111 and clock signal 119 or 121 in phase adjustment means 123.

Therefore, it is useful to eliminate phase shifts caused by fluctuations in temperature or the like or fluctuations in power supply, thereby preventing deterioration of the error rate.

[Embodiment] FIG. 2 shows an embodiment of the present invention. Here, the same reference numerals as in FIG. 4 indicate corresponding blocks, and their details will be omitted here.

In the figure, a clock component included in an input signal 413 is extracted and a clock signal 419 is sent to a variable delay circuit 2'11.
is supplied to This delay circuit 211 has a variable delay time depending on the voltage, and generates three delayed clock signals 213A, 21 with different delay times at equal time intervals.
3B and 213C are output.

In addition, the input signal 413 is used as a "data signal" by the D flip-flops 215A and 215 of the three data identification circuits.
It is commonly supplied to each data input terminal of B and 215C. These three D flip-flops 215A
- C clock input terminal C of three delayed clock signals 2
13A-C and their Q output signals are fed to one input terminal of three error detectors 217A-C.

Further, three delayed clock signals 213A-C are supplied to the other input terminals of these error detectors 217A-C, and these error signals 219A-C are applied to the control circuit 221. This control circuit 221 generates a control signal 223 with variable voltage and supplies it to the variable delay circuit 211 .

A second flip-flop 215 is connected to the data output terminal 225.
The Q output signal of B is output as a data output signal. Further, the second delayed clock signal 213B from the delay circuit 211 is outputted to the clock output terminal 227 as a clock output signal. Furthermore, the error output terminal 229 has a second
The error signal 219B of the error detector 217B is output as an error output signal.

Here, the three D flip-flops 215A to 215C function as data state identification circuits, and the three error detectors 215A to 215C function as data state identification circuits.
1? A-C performs "error detection".

The operation of the above-described configuration will be explained below with reference to the timing diagram of FIG.

The input signal 411 shown in FIG. 3(a) is used as a data signal to identify the data state by three D flip-flops 215A-C.

Now, the three delayed clock signals 213A-C output from the delay circuit 211 are at time A, as shown in FIG.
Assume that B and C stand up respectively. In this case, since the data bit of the input signal 413 falls within the time when the data bit occurs, the data signal and the delayed clock signal 213A-c
are maintained in a relatively appropriate timing relationship.

Therefore, the "errors" of the three error signals 219A-C are the least "errors" of the error signal 219B, the voltage of the control signal 223 is the desired value, and the delay in the delay circuit 211 corresponds to that voltage. It is considered a value.

By the way, for example, for some reason, the delayed clock signal 21
3A-C advance relative to the data signal, and FIG.
Assume that the time relationship is as shown in C1. In this case, the identification of the data state in the 37th flip-flop 215C is correct, but the data identification in the first and second flip-flops 215A and 215B is incorrect, so the third error signal 219C contains the minimum error information. appear.

The three error signals 219A-C are each converted into voltages by the control circuit 221, and the control signal 223 as the voltage signal increases the delay amount of the delayed clock signals 213A-C.

The control circuit 221 has a second error signal 2.
The voltage of the control signal 223 is generated in a direction that minimizes the error in 19B. In other words, the relative timing relationship is compensated by feedback control based on the identification result. Delayed clock signal 213A
-C is delayed and the timing relationship as shown in FIG. 3 (bl) is reached, the compensation operation is stopped.

Next, consider the case where the three delayed clock signals 213A-C are delayed relative to the data signal as shown in FIG. 3(d). In this case, the identification of the data states in the second and third flip-flops 215B and 215C is in an incorrect timing relationship, and the minimum error information appears in the first error signal 219A. In response, the control circuit 221 generates a voltage as the control signal 223 that reduces the amount of delay of the delayed clock signals 213A-C. In this case as well, the control circuit 221 works to minimize the error in the second error signal 219B, and the compensation operation is performed until the timing relationship as shown in FIG. 3(b) is achieved.

Since this automatic clock phase adjustment device performs phase control so that the error of the second error signal 219B is minimized, the Q output signal of the second flip-flop 215B is used as the data output signal, and the second delayed clock signal 213B is Each is output as a clock output signal.

In the above-described embodiment, three delayed clock signals 213A to 213C having different timings are generated, data is identified accordingly, and the phase is automatically adjusted, but the present invention is not limited to this. There isn't. for example,
Two delayed clock signals may be generated, and the phase may be automatically adjusted based on error information at corresponding timings. Further, the determination may be performed based on four or more delayed clock signals each having a different timing.

Furthermore, the input signal 413 side may be delayed, as long as the phases of the data signal and the clock signal are adjusted relatively.

〔Effect of the invention〕

As described in detail above, according to the present invention, the phases of the data signal and the clock signal are always automatically adjusted and controlled based on the error result after data identification. Even if the timing relationship deviates, it is automatically compensated for to an appropriate relative timing relationship. This improves the error rate of data identification and is extremely useful in practice.

[Brief explanation of drawings]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a block diagram showing an embodiment of the present invention, Fig. 3 is a timing explanatory diagram in the embodiment of the present invention, and Fig. 4 is a configuration block diagram of a conventional example. , FIG. 5 is a timing explanatory diagram in a conventional example. In FIG. 1, 111 is an input signal, 115 is a clock extraction circuit, 117 is a data signal, 119.121 is a clock output signal, 127.131 is an identification circuit, and 135 is a control means. In Fig. 2, 211 is a delay circuit, and 215A-C are D flip-flops (data identification circuits).
, 217A-C are error detectors, 219A-C are error signals, 223 is a control signal, and 213A-C are delayed clock signals. Patent applicant: Fujitsu Limited.

Claims (1)

[Claims] A clock extraction circuit (115) that outputs a clock signal (113) from an input signal (111);
13) outputs at least two clock signals (119), (121) having a predetermined timing relationship, and also determines the phase of the input signal of these clock signals and the signal used as the data processing clock signal. phase adjustment means (123) for relatively adjusting the clock signals (119) and (120); and an identification circuit (127) that identifies the data of the input signal for each clock signal (119) and (120) and generates identification signals (125) and (129). , (129); and control means (135) for supplying a control signal (133) for causing the relative position adjustment to the phase adjustment means (123) in response to the identification signals (125), (129). An automatic phase adjustment device characterized by: