JPH02109325A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the reduction in resistance by an etching residue by forming an amorphous silicon layer and conducting the treatment before patterning at a low temperature causing no grain growth. CONSTITUTION:An element separating insulating film 2, a gate insulating film 3, and an amorphous silicon layer 4 are successively formed on the surface of a substrate 1. Then, a high melting point metal silicide film 5 such as WSix, MoSix or TaSix is formed at a low temperature not more than 600 deg.C by CVD process. An impurity such as phosphor is ion-impregnated with such an impregnation energy as to dope the impurity only into the film 5. Then, an insulating film 6 is formed at a temperature not more than 600 deg.C, and then the films 5 and 4 are subjected to photoetching to form a gate electrode. Thereafter, when a diffusion treatment is carried out at a high temperature, the impurity in the film 5 is diffused in the film 4, which film 4 is then made conductive and polycrystallized. Hence, the grain growth is never caused, and the reduction in resistance by the etching residue can be prevented.

Description

[Detailed description of the invention] The present invention will be explained according to the above order.

A. Field of industrial application B9 Summary of the invention C1 Prior art [No. 21m] Problems to be solved by the invention [Fig. 3] Example of means and action for solving the weeding point [Fig. 1] Of the invention Effects (A, Industrial Application Field) The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device in which electrodes are formed of silicon or polycide.

(B. Summary of the Invention) The present invention uses an amorphous silicon film in order to prevent a low breakdown voltage due to etching residue due to grain growth in the method described in 1. The process of forming and buttering the same is carried out at a low temperature that does not cause grain growth.

(C, Prior Art) [Fig. 2] Fig. 2 (A) shows, in order of process, an example of the 7j-method for manufacturing an MO5 type semiconductor device in which the gate quasi-pole is formed using polycide. be.

(A)pa',! forming an insulating film for element-r-isolation by selectively heating and oxidizing the surface portion of the semiconductor substrate a;
Kate insulation JIS! by heating and oxidizing the surface of the element-forming region! C, and then a polycrystalline silicon film d
is formed by CVD. FIG. 2(A) shows the state after the polycrystalline silicon film d is formed.

(B) Next, for example, pre-deposition 1 (POCQ,
) and solid-state diffusion to dope phosphorus into the polycrystalline silicon film d to make the polycrystalline silicon IIQ conductive.

Thereafter, the natural oxide film formed on the surface of the polycrystalline silicon lll2d is removed using, for example, hydrofluoric acid. FIG. 2(B) shows the state after the polycrystalline silicon film d is formed.

<C> Next, as shown in the same figure (C), WSi2゜MoS
;,,, High melting point metal silicide film such as TaSi2 etc.
is formed by CVD or sputtering.

(D) Next, an insulating film e is formed as shown in FIG. This insulating film e is formed to increase the thickness of a sidewall for protecting the side surface of the gate electrode which will be formed later.

(E) Next, polycrystalline silicon I was etched by photoetching.
IQ d , the silicide film e, and the insulation film f are selectively removed to form polycide electrodes d and e as shown in FIG. 2(E).

(F) Next, using the gate electrode-e as a mask, t
The surface of the conductor substrate a is doped with an n-type impurity and the surface of the conductor substrate a is doped as shown in FIG.
N-type regions g and h are formed as shown in F).

(G) Next, an insulating film is formed and by RIE, a sidewall i is formed on the side surface of the gate electrode d as shown in FIG. 3(G).

(H) Next, impurities are doped using the sidewalls i and gate electrodes d as masks, as shown in the figure (H).
As shown in FIG.

For example, g is the source and h is the drain.

(1) Next, as shown in FIG. 12(1), a 7u pole tlQ j , j made of polycrystalline silicon is formed so as to be in contact with the source g and drain h.

(J) Next, interlayer insulation II5! Then, contact holes 1 and 1 are formed by selectively etching as shown in FIG. 2(J).

(K) Next, as shown in FIG.

(D. Problem to be solved by the invention) [Figure 3] By the way, the manufacturing method shown in Figure 2 involves thinning the polycrystalline silicon IIQ d constituting the gate electrode by doping it with impurities. There is a problem that grains of polycrystalline silicon 1 are grown due to the high temperature during predeposition. This is because, in order to miniaturize the element r (1), it is required to reduce the thickness of the polycrystalline silicon film d, for example, it is necessary to make the film thickness 1,500 F or more. However, when ll12J'X is thinned, grains with a diameter larger than that of the film are generated due to the processing temperature (approximately 1000 degrees Celsius) during pre-deposition, resulting in non-negligible protrusions.Figure 3 (A) shows such a protrusion 0. If such a protrusion 0 occurs, etching residue will occur during patterning to form a gate electrode, and this will result as shown in (B) of the same figure. If it occurs near the sidewalls of the gate electrode, it may become a factor that prevents the formation of a sidewall i of sufficient thickness there, resulting in a short circuit between the gate electrodes 1d-e and the source or drain electrodes. This poses a problem in that the withstand voltage becomes low, even if it does not occur.

Therefore, it is conceivable to dope the impurity into the polycrystalline silicon film d by ion implantation, instead of forming a pre-deposition film and solid-diffusing the impurity in the film into the polycrystalline silicon nqd. However, if the polycrystalline silicon film is thin, even if the implantation energy is considerably weakened, it will not be possible to prevent most of the impurities from penetrating through channeling and reaching the channel portion, and the threshold voltage vth
There are problems such as making things go crazy.

In addition, when cleaning with dilute hydrofluoric acid to remove natural oxidation on the surface of the polycrystalline silicon film d after doping with impurities, hydrofluoric acid diffuses from the grain boundaries of the polycrystalline silicon film d and damages the gate insulating film C. There was also the problem that the gate insulating film C was deteriorated by erosion.

The present invention has been made to solve these problems, and it prevents the silicon film from forming grain boundaries and etching residue due to high-temperature treatment, thereby preventing a reduction in breakdown voltage. EJ is to prevent deterioration during cleaning.

(E. Means for Solving the Problems) In order to solve the problems described in item t, the method for manufacturing a semiconductor device of the present invention forms an amorphous silicon film and performs a process of buttering it to cause grain growth. It is characterized by being carried out at low temperatures.

(F. Effect) According to the method for manufacturing a semiconductor device of the present invention, since an amorphous silicon film is formed, the channeling effect can be made much smaller than in the case of polycrystalline silicon. Therefore, when the silicon film is doped with impurities to make it conductive, there is no possibility that the impurities will pass through the silicon film and invade the surface portions of the J and ζ plates. Further, since the silicon film is amorphous, there is no possibility that a cleaning solution such as hydrofluoric acid will pass through the silicon film. Therefore, the cleaning solution 5 cleans the silicon film.
It can prevent the land from being eroded.

Furthermore, since the silicon film is not subjected to heat treatment at a high temperature that would cause grain growth in the process of buttering the silicon film, there is no etching residue at all. Therefore, it is possible to eliminate the risk of a drop in breakdown voltage due to etching residue.

(G, Embodiment) [First I-Me 1] Hereinafter, a method for manufacturing a semiconductor device of the present invention will be described in detail according to the illustrated embodiment.

FIGS. 1(A) to 1(A) are sectional views showing one embodiment of the manufacturing method of the r-conductor device of the present invention in the order of steps.

(A) p type! By selectively heating and oxidizing the surface portion of the i-conductor substrate 1, the element layer insulation 11q2 is formed, and the element f
Gate insulation +1 by heating and oxidizing the surface of the formation region
423 is formed, and then an amorphous silicon film 4H is formed.
IAJ', (fii ~ several thousand people) 4 is formed by low pressure CVD (processing temperature 600°C or higher, for example 550°C). Note that the amorphous silicon film 4 may be formed by sputtering. Figure 1 (A) shows amorphous silicon I! 24 is shown after formation.

(B) Next, as shown in the same figure (B), WSix, MoS
A high melting point metal silicide rA5 such as ix or T a S i x is formed by a CVD method or a sputtering method. What is important here is that the treatment temperature should be 550°C if it is 600°C or higher. This is because if the processing temperature is higher than 600° C., there is a risk that the amorphous silicon III24 will grow into grains. Further, it is preferable that the high melting point metal silicide film 5 is also formed in an amorphous state. This is because amorphous materials have a stronger channeling prevention effect. In order to form the high melting point metal silicide film 5 in an amorphous state, it is preferable to use a low pressure CVD method.

(C) Next, as shown in FIG. 1(C), for example, phosphorus P
Impurities such as the following are implanted by ion implantation. By setting the implantation energy to an appropriate value, it is possible to ensure that the impurity is toped only into the refractory metal silicide IIQ5. Of course, the amorphous silicon rA4 may also be doped, but in this embodiment, in order to more completely prevent channeling, only the amorphous silicon 11!24 is doped with impurities at this stage. The impurities in the high-melting point metal silicide film 5 are diffused into the amorphous silicon film 4 by heat treatment after completing the buttering for electrode formation, thereby making the amorphous silicon film 4 conductive. That's how I do it.

(D) Next (, as shown in Figure 1 (D), insulate q6 with C
Formed by VD. In this case as well, CVD is performed at a temperature of 600° C. or higher.

(E) Next, as shown in FIG. 3E, the insulating film 6, high melting point metal silicide film 5, and amorphous silicon film 4 are patterned by photoetching (to form a gate electrode).

After that, manufacturing is carried out in the same manner as the manufacturing method of a normal MOS'l'-conductor device. After completing the patterning for forming the gate electrode, there is no longer a restriction that the processing must be performed at a temperature of 600° C. or lower, which is a low temperature that does not cause grain growth of amorphous silicon III2. For example, 700℃ exceeding 600℃
When processing (for example, diffusion treatment) was performed at a high temperature of ~1100°C, impurities in the high melting point metal sysosite film 5 diffused into the amorphous silicon film 4 and the amorphous silicon film 4 became conductive. Moreover, the amorphous silicon film 4 becomes polycrystalline silicon.

According to this method of manufacturing a semiconductor device, after the amorphous silicon film is formed and before etching the high melting point metal silicide film for forming the gate'its and the amorphous silicon film, the etching process is performed at a temperature exceeding 600°C. Since this process is not performed, there is no risk of grain growth occurring in the amorphous silicon film, and furthermore, there is no risk of forming etching residues when the amorphous silicon IIQ and high melting point metal silicide films are etched later. Therefore, as shown in FIG. 3 (CB), it is possible to eliminate the problem of insufficient thickness of the side wall on the side surface of the gate electrode due to etching residue, resulting in insufficient withstand voltage and defects.

The silicon film 4 is amorphous at the stage where 1 J of impurity ions are implanted, and moreover, silicon Il! 24
On top of the high melting point metal silicide flu 5, which is also in an amorphous state, is formed, and the impurity ions are implanted into the high melting point metal silicide.
It is done in L/. Therefore, it is possible to do impurity doping to lower the resistance of the amorphous silicon film without causing channeling.

After forming silicon JIQ4, high melting point metal silicide Jl! is applied to the surface of silicon film 4 without doping with impurities. ;! 5 is formed, there is no need for cleaning the natural oxide film on the surface of the silicon film 4 with hydrofluoric acid.

Therefore, there is no possibility that the problem of hydrofluoric acid passing through the silicon film 4 and reaching the F-based gate insulating film 3 and deteriorating it will occur.

In this embodiment, the present invention was applied to a method for manufacturing an MO5 type semiconductor device in which a gate electrode was formed using a volisard. The present invention can also be applied to a method of manufacturing a semiconductor device.In this case as well, the silicon film forming the gate electrode is initially formed in an amorphous state, and its illumination is
An insulating film is formed by cVD, and impurities are doped by implanting ions through the insulating film.

Furthermore, since the channeling effect of the amorphous silicon film is weak, it is possible to effectively prevent impurities from entering the channel. Of course, it goes without saying that high-temperature treatment that would cause grain growth in the silicon film is not performed until the amorphous silicon film is buttered by etching. Furthermore, even if cleaning with hydrofluoric acid or the like is performed, the cleaning liquid does not easily penetrate into the amorphous silicon 11q, so there is little risk that the underlying layer will be eroded by the cleaning liquid.

(H. Effect of the invention) As described above, the method for manufacturing a semiconductor device of the present invention includes:
An amorphous silicon film is formed by CvD at a low temperature that does not cause grain growth, and an impurity doping process to make the amorphous silicon film conductive is performed at a low temperature that does not cause grain growth.
This method is characterized in that electrodes are formed by selectively etching an amorphous silicon film.

Therefore, according to the method of manufacturing a semiconductor device of the present invention, since an amorphous silicon film is formed as silicon M, the channeling effect can be made much smaller than in the case of polycrystalline silicon. Therefore, when the silicon film is doped with impurities to make it conductive, there is no possibility that the impurities will pass through the silicon film and enter the substrate side. Furthermore, since the silicon film is amorphous, there is no possibility that a cleaning solution such as hydrofluoric acid will pass through the silicon film. Therefore, it is possible to prevent the underlying silicon IIQ from being eroded by the cleaning liquid.

Furthermore, since the silicon film is not subjected to heat treatment at a high temperature that would cause grain growth, there is no etching residue at all. Therefore, it is possible to eliminate the problem of low breakdown voltage I8 due to etching residue.

A cross-sectional view showing one embodiment of the manufacturing method in the order of steps; FIGS.
Figures (A) and (B) are cross-sectional views showing the problem.

Explanation of symbols 4... (amorphous) silicon film.

[Brief explanation of the drawing]

Figures 1 (A) to (E) show the procedures for the semiconductor device of the present invention. 2. Name of the invention Method for manufacturing semiconductor devices 3. Relationship with the person making the amendment Patent applicant address 6-7-35, Kitashinyo, Tokyo Parts Store Name (2)
18) Sony Corporation 4, Agent Address: 2-53-5-6, Nishi-Nippori, Arakawa-ku, Tokyo, Contents of the Amendment (1) "In the description tube, page 11, lines 18 to 19,"
Correct "was done" to "has been done." (2) Replace the drawings (A) and (B) with the attached corrected drawings (A) and (B). 7. List of attached documents (1) Corrected drawings [Fig. 3 (A), (B)]...11 1.39- (A> (B) Cross-sectional view showing the problem Fig. 3)

Claims (1)

[Claims] (1) An amorphous silicon film is formed by CVD at a low temperature that does not cause grain growth, and an impurity doping process is performed to make the amorphous silicon film conductive at a low temperature that does not cause grain growth. A method for manufacturing a semiconductor device characterized by forming electrodes by selectively etching an amorphous silicon film