JP2003068895A - Method for manufacturing semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor storage device capable of reducing a margin fault due to shorting of metal wiring and the high resistance of a gate electrode by preventing a metal electrode from being oxidized in a heat treating step at the time of forming a sidewall of a gate electrode. SOLUTION: The method for manufacturing the semiconductor storage device comprises the steps of forming a nitride film 113 on an upper layer of a metal electrode layer 111 on a gate electrode layer, and removing a gate oxide film 106 under etching conditions in which an etching rate of the nitride film 113 is slower than that of the film 106 in a source region forming step. Thus, since the nitride film 113 is retained on the metal electrode layer even when the film 106 is removed in the source region forming step, the metal electrode layer 111 can be prevented from being oxidized in the later heat treating step.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor memory device using a self-aligned source region forming method.

[0002]

2. Description of the Related Art Conventionally, in a non-volatile memory such as an EPROM, an EEPROM and a flash memory, in order to suppress an increase in cell area, its own gate electrode is used as a mask to form a common source region of a plurality of memory cells. A self-aligned source forming method (self-aligned source) has been used. In the self-aligned source process, after the gate electrode is formed, etching is performed using a photoresist pattern for a self-aligned source, which is patterned so that the drain region is covered and only the source region is exposed. The isolation oxide film is removed to form a common source region.

A conventional wafer process flow for manufacturing a flash memory will be described with reference to FIG.
Note that here, the gate electrode (floating gate 1
07 + interlayer insulating film 109 + control gate 110)
The manufacturing method after forming the metal electrode layer (for example, tungsten silicide WSi ₂ ) 111 for lowering the resistance of the gate electrode will be described above, and the description of the manufacturing steps before that will be omitted.

An oxide film 112 is formed on the metal electrode layer 111 by the CVD method, a photoresist is uniformly applied on the oxide film 112, and then photolithography is performed to form a resist pattern 114 for the gate electrode. Form (Fig. 12
(A)). Next, the floating gate 107, the interlayer insulating film 109, the control gate 110, the metal electrode layer 111, and the oxide film 112 are etched to form a gate electrode pattern, and the resist pattern 114 is removed.
Then, using the obtained gate electrode pattern as a mask,
By implanting ions into the surface of the wafer (silicon substrate) 101, the source region 134s of the flash memory,
The drain region 134d is formed (FIG. 12B).

Next, in order to form the common source portion of the flash memory in a self-aligned manner by using the gate electrode pattern as a mask, a resist pattern 115 is formed by photolithography up to about half of the gate, and the source region is formed. The gate oxide film 106 and the element isolation oxide film (not shown) on the surface of the wafer 101 are removed by dry etching while ion implantation is performed on the portion to be the target (FIG. 12C).

After that, the resist pattern 115 is removed, and heat treatment is performed at about 900 ° C. with N ₂ and O ₂ ,
The source / drain of the flash memory is diffused, and the side wall portion 116 of the flash memory is formed (FIG. 12D).

[0007]

However, according to this conventional technique, when the source region is formed in a self-aligned manner by utilizing its own gate electrode, the gate electrode is etched when the element isolation oxide film and the gate oxide film 106 are etched. The oxide film 11 in the portion where the upper resist pattern 115 is not provided
2 is removed, and the metal electrode layer 111 near the source is removed.
However, there is a problem that a bare area is formed (portion (1) in FIG. 12C). Metal electrode layer 11
1 is exposed, as shown in the enlarged cross-sectional view of FIG. 13, the metal electrode layer 1 exposed in the subsequent heat treatment step.
11 is easily oxidized by O ₂ gas, and the metal electrode layer 11
Since 1 expands, there is a problem that a step is formed on the base of the metal wiring, causing a short circuit of the metal wiring. In addition, since the resistance value of the metal electrode layer 111 is increased, there is a problem that a high resistance of the gate electrode causes a margin failure.

The present invention has been made in view of the above, and prevents the metal electrode layer provided on the gate electrode from being oxidized in the heat treatment process of the gate electrode, thereby short-circuiting the metal wiring and the gate. It is an object of the present invention to provide a method of manufacturing a semiconductor memory device capable of reducing margin failure due to high resistance of electrodes.

[0009]

A step of forming a gate electrode pattern on a semiconductor substrate, and an oxide film is etched from the surface of the semiconductor substrate to be a source region using the gate electrode pattern as a mask. In the method of manufacturing a semiconductor, including a self-aligned source forming step of forming a self-aligned source by removing the metal electrode on the gate electrode layer, and a heat treatment step of heat treating the semiconductor substrate. And a nitride film is provided on the metal electrode layer.

According to the present invention, by forming the nitride film on the metal electrode layer on the gate electrode, the selectivity of the gate electrode portion and the oxide film by etching is increased in the subsequent self-aligned source forming step. Because you can
Even after the oxide film is removed from the surface of the semiconductor substrate to be the source region, the nitride film on the metal electrode layer can be left. Therefore, the metal electrode layer on the gate electrode is not exposed even after the oxide film is etched, and it is possible to prevent the metal electrode layer from being oxidized in the subsequent heat treatment step.

In the method of manufacturing a semiconductor memory device according to the next invention, in the above invention, in the self-aligned source forming step, the oxide film is formed under an etching condition in which an etching rate of the nitride film is slower than that of the oxide film. Is removed.

According to the present invention, the nitride film is formed on the upper layer of the metal electrode layer, and the gate oxide film is removed under the etching condition that the etching rate of the nitride film is slower than that of the gate oxide film in the source region forming step. In the subsequent self-aligned source forming step, the selection ratio by etching the gate electrode and the oxide film can be further improved.

A semiconductor memory device manufacturing method according to the next invention is characterized in that, in the above invention, the gate electrode layer has a floating gate, an insulating film and a control gate.

According to the present invention, the gate electrode layer is configured to include the floating gate, the insulating film and the control gate. With this configuration, a flash memory can be obtained.

A method of manufacturing a semiconductor memory device according to the next invention is characterized in that, in the above invention, a protective oxide film is provided between the metal electrode layer and the nitride film.

According to the present invention, the protective oxide film is further provided between the metal electrode layer and the nitride film. Therefore, stress generated between the metal electrode layer and the nitride film can be prevented, and reliability of electric characteristics of the transistor can be improved.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of a method for manufacturing a semiconductor memory device according to the present invention will be described in detail below with reference to the accompanying drawings.

1 to 11 are process sectional views showing a method of manufacturing a semiconductor memory device (NOR flash memory) according to an embodiment of the present invention.

FIG. 1 is a view showing the wafer after formation of the resist pattern 104, and FIG. 1 (a) is a plan view.
(B) is a cross-sectional view taken along the line AA 'of (a), (c) is B of (a).
It is a -B 'sectional view. Further, AA ′ and BB ′ indicating the cross-sectional position are attached to the left side of each of FIGS. 1 to 11. In addition, in FIGS. 1 to 11, the area on the left side on the wafer is an area in which a control circuit of the flash memory is created, and a description of this area will be omitted. First, as shown in FIG. 1, 800 to 900 are formed on the main surface of the wafer 101.
An oxide film (SiO ₂ ) 102 is formed with a gas such as H ₂ O _{2 at} about ° C. A nitride film 103 is formed thereon by using the CVD method. After that, a resist pattern 104 for selectively oxidizing the active region and the element isolation region is formed by photolithography.

Using the resist pattern 104 as a mask,
The oxide film 102 and the nitride film 103 in the portion to be the element isolation region 105 are etched with a gas such as CF ₄ . After etching, the unnecessary resist pattern 104 is removed and impurities on the wafer are washed. The cleaned wafer is placed in an oxidation furnace, and a relatively thick silicon oxide film is selectively oxidized and grown on the surface of the wafer 101 by using the nitride film 103 having oxidation resistance as a mask to form the element isolation region 105.
To form. The remaining nitride film 103 is removed using hot phosphoric acid. FIG. 2 is a view showing the wafer after the formation of the element isolation region 105.

Next, the well 132 is formed in the flash memory portion by the ion implantation method. Also, ion implantation for channel doping that determines the threshold voltage is performed (FIG. 3). 133 is a bottom well.

After removing the resist pattern 104,
After removing the oxide film 102 remaining on the surface of the wafer 101 with a hydrofluoric acid solution, a gate oxide film 106 of the flash memory is formed on the entire surface with a gas such as H ₂ O ₂ gas at 700 ° C. to 900 ° C. After that, a P (phosphorus) -doped Si film 107 is formed on the entire surface by the CVD method. The Si film 107
Is the floating gate of the flash memory. Next, a resist pattern 108 for leaving a portion to be a floating gate of the flash memory is formed by photolithography. FIG. 4 is a diagram showing the wafer after the resist pattern 108 is formed.

After forming the resist pattern 108, C
The Si film 107 is etched with a gas such as F ₄ .
The resist pattern 108 is removed. As a result, the floating gate pattern 107 is formed as shown in FIG.

Next, as shown in FIG. 6, an interlayer insulating film 109 of the flash memory is formed on the floating gate 107 and the element isolation region 105. Interlayer insulating film 109
Can be formed by an oxidation method, a CVD method, or the like.
A polycrystalline silicon film doped with an N-type conductivity type impurity such as phosphorus or arsenic is formed on the interlayer insulating film 109 by the CVD method. The polycrystalline silicon film doped with phosphorus or the like becomes the control gate 110. On the polycrystalline silicon film 110 doped with phosphorus or the like, a metal electrode layer 111 (WSi ₂ or the like) for lowering the resistance value of the gate electrode is formed by sputtering, CVD method or the like. Then, the protective oxide film 1 is formed on the metal electrode layer 111 by the CVD method.
12 and the nitride film 113 are formed. Providing the nitride film 113 can increase the selection ratio by etching the gate electrode in a later step. In addition, the metal electrode layer 1
11 is provided between the nitride film 113 and the nitride film 113, the stress generated between the metal electrode layer 111 and the nitride film 113 can be prevented, and the reliability of the electrical characteristics of the transistor is improved. be able to. Then
A resist pattern 114 for obtaining a desired gate electrode pattern is formed on the nitride film 113 by photolithography.

By utilizing this resist pattern 114,
Anisotropic etching of the nitride film 113 is performed using a gas such as CF ₄ . After removing the resist pattern 114, the protective oxide film 112, the metal electrode layer 111, the control gate layer 110, the interlayer insulating film 109, and the floating gate 107 are etched using the remaining pattern of the nitride film 113 as a mask to form the gate electrode. Form a pattern. Then, using the obtained gate electrode pattern as a mask, ions are implanted into the surface of the wafer 101 to form a source region 134s and a drain region 134d of the flash memory. FIG. 7 shows a cross-sectional view of the wafer after ion implantation.

In order to form the source portion of the flash memory in a self-aligned manner by using the gate electrode pattern as a mask, up to about half the control gate,
A resist pattern 115 is formed by photolithography so that the drain region is covered and only the source region is exposed.
Then, etching is performed using the resist pattern 115 for the self-aligned source to remove the element isolation region 105 and the gate oxide film 106 remaining in the source region with a gas such as CF ₄ to expose the wafer 101. . A common source region is formed by performing ion implantation on the source region 134s where the wafer 101 is exposed. FIG. 8 shows a cross-sectional view of the wafer after forming the common source region.

In the present invention, the nitride film 11 is used for this etching rather than the element isolation region 105 and the gate oxide film 106.
No. 3 is characterized in that the condition that the etching rate is slower is applied. For example, the etching rate of the nitride film 113 can be made slower than that of the gate oxide film 106 by etching using an etching gas having the following composition.

Etching gas 1 C ₅ F ₈ (10 cc) + CO (20 cc) + Ar (350
cc) + O ₂ (5cc)

Etching gas 2 C ₄ F ₆ (10 cc) + CO (20 cc) + Ar (35
0cc) + O ₂ (5cc)

In the present invention, the condition that the nitride film 113 has a slower etching rate than the gate oxide film 106 is applied. Therefore, even after the gate oxide film 106 is removed, the surface of the metal electrode layer 111 is not exposed. And is protected by a nitride film 113. Therefore, it is possible to prevent the metal electrode layer 111 from being oxidized in the subsequent heat treatment step.

Conventionally, since the nitride film 113 is not provided on the gate electrode, the oxide film 112 on the gate electrode in the portion where the resist is not provided is completely removed by etching the gate oxide film 106. A region where the metal electrode layer 111 near the source was exposed was likely to occur (portion (1) in FIG. 12C). Therefore, in the subsequent heat treatment step, the bare metal electrode layer 111 is easily oxidized by O ₂ gas (FIG. 13), the metal electrode layer 111 expands, and a step difference in the metal wiring base is generated, which causes a metal wiring. However, there is a problem in that the resistance value of the metal electrode layer 111 increases due to the oxidation, which causes a margin failure due to the increase in the resistance of the gate electrode. The present invention solves these problems.

After removing the resist pattern 115,
In order to diffuse the source / drain of the flash memory and form an oxide film 116 on the sidewall of the flash memory, heat treatment is performed with N ₂ and O ₂ at around 900 ° C. (FIG. 9). At this time, as shown in FIG. 14, since the surface of the metal electrode layer 111 in the source region is protected by the nitride film 113, the metal electrode layer 111 is less likely to be oxidized.

Next, an oxide film 117 is formed by the CVD method. The oxide film 117 is formed of aluminum wiring 119.
It becomes the groundwork of. On the oxide film 117, a resist pattern 118 for forming a contact hole is formed by photolithography in the drain region 134d which is in contact with the aluminum wiring (FIG. 10).

A contact hole 117a is formed in the oxide film 117 using the resist pattern 118, and then the resist pattern 118 is removed. Further, an aluminum film to be wiring is deposited on the entire surface of the wafer by a sputtering method, and a pattern of aluminum wiring 119 is formed by photolithography. Further, in order to protect the wafer, a surface protection film 120 such as a silicon oxide film is formed on the aluminum wiring 119 (FIG. 11).

[0035]

As described above, according to the present invention, by forming the nitride film on the metal electrode layer on the gate electrode, the self-aligned source forming step is performed later.
Since the selection ratio between the gate electrode portion and the oxide film can be increased by etching, the nitride film on the metal electrode layer can be left even after the oxide film is removed from the surface of the semiconductor substrate to be the source region. Therefore, the metal electrode layer on the gate electrode is not exposed even after the oxide film is etched,
It is possible to prevent the metal electrode layer from being oxidized in the subsequent heat treatment process.

According to the next invention, the nitride film is formed on the upper layer of the metal electrode layer, and the gate oxide film is removed under the etching condition that the etching rate of the nitride film is slower than that of the gate oxide film in the source region forming step. As a result, it is possible to further improve the selection ratio by etching the gate electrode and the oxide film in the subsequent self-aligned source forming step.

According to the next invention, since the gate electrode layer has the floating gate, the insulating film and the control gate, the obtained transistor becomes a flash memory.

According to the next invention, since the protective oxide film is provided between the metal electrode layer and the nitride film, the stress generated between the metal electrode layer and the nitride film can be prevented,
The reliability of electric characteristics of the transistor can be improved.

[Brief description of drawings]

FIG. 1 is a process cross-sectional view showing the method of manufacturing a semiconductor memory device of the present embodiment.

FIG. 2 is a process cross-sectional view showing the method of manufacturing the semiconductor memory device of the present embodiment.

FIG. 3 is a process cross-sectional view showing the method of manufacturing the semiconductor memory device of the present embodiment.

FIG. 4 is a process cross-sectional view showing the method of manufacturing the semiconductor memory device of the present embodiment.

FIG. 5 is a process cross-sectional view showing the method of manufacturing the semiconductor memory device of the present embodiment.

FIG. 6 is a process cross-sectional view showing the method of manufacturing the semiconductor memory device of the present embodiment.

FIG. 7 is a process cross-sectional view showing the method of manufacturing the semiconductor memory device of the present embodiment.

FIG. 8 is a process cross-sectional view showing the method of manufacturing the semiconductor memory device of the present embodiment.

FIG. 9 is a process cross-sectional view showing the method of manufacturing the semiconductor memory device of the present embodiment.

FIG. 10 is a process cross-sectional view showing the method of manufacturing the semiconductor memory device of the present embodiment.

FIG. 11 is a process cross-sectional view showing the method of manufacturing the semiconductor memory device of the present embodiment.

FIG. 12 is a process sectional view showing the method of manufacturing the conventional semiconductor memory device.

FIG. 13 is an enlarged cross-sectional view of a flash memory obtained by a conventional method for manufacturing a semiconductor memory device.

FIG. 14 is an enlarged cross-sectional view of a flash memory obtained by the method of manufacturing a semiconductor memory device according to the present invention.

[Explanation of symbols]

101 wafer, 102 oxide film, 103 nitride film, 1
04 resist pattern, 105 element isolation region, 10
6 gate oxide film, 107 floating gate (S
i film), 108 resist pattern, 109 interlayer insulating film, 110 control gate (polycrystalline silicon film), 111 metal electrode layer, 112 protective oxide film, 11
3 nitride film, 114 resist pattern, 115 resist pattern, 116 sidewall portion (oxide film), 117 oxide film, 117a contact hole, 118 resist pattern, 119 aluminum wiring, 120 surface protective film, 132 well, 133 bottom well, 134
s Source region, 134d Drain region.

Claims (4)

[Claims] 1. A gate electrode pattern forming step of forming a gate electrode pattern on a semiconductor substrate, and etching and removing an oxide film from the surface of the semiconductor substrate to be a source region, using the gate electrode pattern as a mask. According to the method of manufacturing a semiconductor, including a self-aligned source forming step of forming a self-aligned source and a heat treatment step of heat-treating the semiconductor substrate, the gate electrode pattern has a metal electrode layer on the gate electrode layer. And a nitride film is provided on the metal electrode layer. 2. The semiconductor memory according to claim 1, wherein, in the self-aligned source forming step, the oxide film is removed under etching conditions in which the etching rate of the nitride film is slower than that of the oxide film. Device manufacturing method. 3. The method of manufacturing a semiconductor memory device according to claim 1, wherein the gate electrode layer has a floating gate, an insulating film, and a control gate. 4. Between the metal electrode layer and the nitride film,
The method for manufacturing a semiconductor memory device according to claim 1, further comprising providing a protective oxide film.