JP2002314064A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device which hardly generates peeling of a layer insulation film. SOLUTION: The method comprises a process for forming a polycide film on a substrate surface, wherein a desired element region is formed, via a gate oxide film, a boron ion implantation process for ion implantation of boron or boron fluoride in the polycide film, a process for forming a gate electrode by patterning the polycide film, a process for ion implantation of impurities by using the gate electrode as a mask and forming a source/drain diffusion layer, a process for depositing a layer insulation film, and a process for carrying out heat treatment for making the layer insulation film dense.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a step of forming a gate electrode by patterning a polycide film. About prevention.

[0002]

2. Description of the Related Art As VLSIs (Very Large Scale Integrated Circuits) and the like are being miniaturized and highly integrated, the resistance of gate electrode wiring is reduced when manufacturing these semiconductor devices. There has been proposed a method of using a polycide film as a gate electrode in which a metal silicide film is formed. In this method, after patterning of a gate electrode, ion implantation for forming a source / drain region is performed, and then an interlayer insulating film is deposited by a CVD method.

In the manufacturing process of such a semiconductor device, when a heat treatment is performed after an interlayer insulating film is deposited, it is often between the polycrystalline silicon film and the metal silicide film or between the metal silicide film and the interlayer insulating film. Peeling occurs. It is considered that this peeling is mainly caused by a difference in coefficient of thermal expansion between the metal silicide and the polycrystalline silicon or the interlayer insulating film, or a weak adhesion.

However, such peeling of the metal silicide film hardly occurs in the element region in which the polycide film is patterned to a fine width, and the peeling actually occurs only when the polycide film remains in a large width without being patterned. Area.

That is, as shown in FIG. 9, a gate electrode of a polycide film is formed in a pattern only in a patterning region 22 usually indicated by oblique lines in a silicon wafer, and the polycide film remains in an outer peripheral portion 23 without being patterned.
That is, as shown in FIG.
A gate oxide film 32 is formed on one surface, and a polycrystalline silicon film 33 and a metal silicide film 34 such as WSi are formed on the gate oxide film 32. Then, the polycide film is patterned only in a certain area required as an element chip in the wafer. Is done.

Then, subsequent ion implantation is also performed only on the element region inside the wafer, and the source / drain diffusion layer 35 is formed.

[0007] Thereafter, as shown in FIG.
An interlayer insulating film 35 such as PSG is deposited, and a heat treatment at about 850 ° C. is performed by a method such as lamp annealing.

In the heat treatment step of the interlayer insulating film 35, as shown in FIG. 10B, the metal silicide film 34 is apt to peel off in the region where the polycide film is not patterned on the outer peripheral portion of the wafer. It is considered that this is because a large area of the polycide film remains on the outer peripheral portion of the wafer, so that a large stress concentration tends to occur in a portion having a weak adhesion or a portion having an abnormal layer in the heat treatment process.

However, even if the metal silicide film peels off at the outer peripheral portion of the wafer, the patterning region 22 shown in FIG. 9 which is actually cut out as a chip does not immediately become defective. However, if left unattended, the peeling may be transmitted to the internal patterning region 22. Conventionally, in order to prevent this, it has been necessary to perform a scrubber treatment on the wafer when peeling has occurred to remove the polycide film in the peeled portion.

Therefore, there has been proposed a method in which the polycide film is patterned in the outer peripheral portion of the wafer in the same manner as in the inner portion, so that stress concentration on the metal silicide film in the subsequent heat treatment step is avoided, and peeling is effectively suppressed.

A method has also been proposed in which ions are implanted in the outer peripheral portion of the wafer in the same manner as in the inner portion, and ions are implanted into the metal silicide film, thereby relaxing the stress of the metal silicide film in the subsequent heat treatment step. (Japanese Patent Laid-Open No. 5
-124675).

It is stated that this ion implantation can prevent peeling for the following reasons. This is because the crystallized metal silicide film becomes amorphous by ion implantation. Impurities enter the lattice defects of the metal silicide film, and volume shrinkage due to disappearance of the lattice defects generated in a later heat treatment step is suppressed. The abnormal species on the metal silicide film are repelled by the ion implantation, and the stress concentration caused by the abnormal layer is eliminated.

[0013]

However, in recent years, when heat treatment of an interlayer insulating film is performed, heat treatment at 900 to 950 ° C. is performed to planarize the surface, thereby forming a denser and flatter interlayer insulating film. I knew I could do it.

On the other hand, there has been a new problem that peeling is more likely to occur as the heat treatment temperature increases. In particular, it has been found that peeling is more likely to occur in the NMOS region.

The present invention has been made in view of the above circumstances, and has as its object to provide a highly reliable semiconductor device in which an interlayer insulating film is hardly peeled off.

[0016]

According to a first aspect of the present invention, there is provided a step of forming a polycide film via a gate oxide film on a substrate surface on which a desired element region is formed, and forming boron or fluoride in the polycide film. A boron ion implantation step of implanting boron, a step of patterning the polycide film to form a gate electrode, a step of implanting impurities by using the gate electrode as a mask to form a source / drain diffusion layer, The method includes a step of depositing a film and a step of performing a heat treatment for densifying the interlayer insulating film.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, the step of performing the heat treatment includes:
It is a high-temperature heat treatment step of maintaining the temperature at 900 ° C. or higher for a predetermined time.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device according to the first or second aspect, the step of forming the source / drain region is a step of implanting N-type impurity ions.

Preferably, the step of performing the heat treatment comprises:
This is a high-temperature heat treatment step of maintaining the temperature at 50 ° C. or higher for a predetermined time.

According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the first to third aspects, the step of depositing the interlayer insulating film includes the step of forming a BPSG film by vapor phase growth. There is a feature.

[0021]

From the results of various experiments, there is a great difference in the effect of preventing peeling depending on the type of ions to be implanted. Implanting boron or boron fluoride into the NMOS region is effective in preventing peeling. It turned out to be more effective.

The present invention has been made in view of this point. By implanting boron or boron fluoride into a metal silicide layer on the NMOS region side,
It is possible to provide a more reliable semiconductor device with an enhanced peeling prevention function.

That is, a flat interlayer insulating film having excellent insulating properties can be formed at low cost and with a short lead time.

[0024]

1 (a) to 1 (g) are main views showing a semiconductor device according to an embodiment of the present invention.
This method is characterized in that boron ions are implanted into the NMOS region, and the entire periphery of the chip is removed from the polycide film by light exposure.

First, as shown in FIG. 1A, a gate oxide film 12 is formed on the surface of a silicon substrate 11 separated into a desired element region by an element isolation region.

Then, as shown in FIG. 1B, a polycrystalline silicon layer having a thickness of about 150 nm is formed on the upper layer by the CVD method. Further, a film thickness of 1
A WSi film 14 of about 00 nm is formed. And BF
₂ ⁺ 20 keV ions, after ions are implanted at a dose of 2 × 10 ¹⁵ cm ^-2, to form a gate electrode by patterning. At this time, a mask pattern is formed so that the polycrystalline silicon film and WSi are all removed from the outer peripheral portion of the wafer.

After that, as shown in FIG. 1C, first, BF ₂ ⁺ ions are implanted on the PMOS side with a gate electrode as a mask at 20 keV and a dose of 2 × 10 ¹³ cm ⁻² to form a shallow low-concentration region. Form 15L.

Next, as shown in FIG. 1D, 40 ions of As ions are formed on the NMOS side using the gate electrode as a mask.
V ions are implanted at a dose of 4 × 10 ¹² cm ⁻² to form a shallow low-concentration region 15L.

Further, as shown in FIG.
A silicon oxide film is formed, and the entire surface is etched to leave the silicon oxide film only on the side wall of the gate electrode, thereby forming a spacer S.

Thereafter, using the spacer and the gate electrode as a mask, first, using the gate electrode as a mask on the PMOS side, a dose of 2 × 10 ¹⁵ cm ⁻² and a B voltage of about 20 keV are used.
F ₂ ⁺ ions are implanted into the source / drain diffusion layer 15.
To form

Next, as shown in FIG. 1F, a dose of 2 × 10 ¹⁵ cm is set on the NMOS side using the gate electrode as a mask.
The source / drain diffusion layer 15 is formed by ion implantation of As ions in the order described above.

Then, as shown in FIG.
After annealing for 10 seconds, an 800 nm-thick BPSG film 16 is formed by a CVD method.

Then, 9 for making the BPSG film denser
Heat treatment is performed at 50 ° C. for 10 seconds.

As described above, it is possible to provide a good semiconductor device having the LDD structure and without film peeling.

When the WSi surface is observed by SEM, the NMOS region has larger grains than the PMOS region.

When boron ions are not implanted in the NMOS region, as shown in FIGS. 2A and 2B,
Peeling is observed only in the NMOS region. In the first place WS
Since the grain size of i is larger on the NMOS side than on the PMOS side, peeling tends to occur from the grain boundary when heat treatment is performed.

On the other hand, in the PMOS region, since the grains were relatively small, peeling was not a problem.

In the NMOS region into which B ions have been implanted, as shown in FIG. 3, the outermost surface of the grain becomes small, and the boundary is separated from the grain boundary as a starting point.
Since it did not reach the Si surface, the grains did not peel off. In other words, in the present invention, the NMOS region has a two-layer structure in which the grain size is two layers, that is, a portion located in the upper layer and having a smaller grain boundary interval and a portion located in the lower layer having a larger grain size. It has a structure.

Further, a photograph by TEM observation of a conventional example is shown. In the left A region, an NMOS region is formed, and in the right B region.
Although a PMOS region is formed in the region, the crystal size is larger on the NMOS side.

FIG. 5 shows a part of the sectional structure of the semiconductor device. As is clear from this figure, polysilicon and WS
It can be seen that peeling has occurred between i.

FIG. 6 shows a state in which peeling has further occurred after the heat treatment.

FIGS. 7 and 8 show sectional structure photographs of the NMOS and PMOS sides of the semiconductor device thus formed. As is clear from the comparison between FIG. 7 and FIG. 8, it can be seen that the grain size is larger on the NMOS side than on the PMOS side.

[0043]

According to the present invention, when an NMOS transistor is formed, B ions or BF ₂ ⁺ ions are
By punching into the gate electrode, a structure with little film peeling can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the present invention;

FIG. 2 is a diagram for explaining the operation and effect of the semiconductor device according to one embodiment of the present invention;

FIG. 3 is a diagram for explaining the operation and effect of the semiconductor device according to the embodiment of the present invention;

FIG. 4 is a comparative view of the surface of the semiconductor device according to the embodiment of the present invention;

FIG. 5 is a schematic sectional view of a semiconductor device according to one embodiment of the present invention;

FIG. 6 is a schematic view showing a peeled state of a semiconductor device of a conventional example.

FIG. 7 is a cross-sectional view of a conventional NMOS region.

FIG. 8 is a cross-sectional view of a conventional PMOS region.

FIG. 9 is a top view of a conventional wafer,

FIG. 10 is a diagram showing a conventional wafer manufacturing process.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Silicon wafer 12 ... Element isolation insulating film 14 ... Source / drain diffusion layer 16 ... BPSG layer

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 4M104 AA01 BB01 CC05 DD37 DD43 DD55 EE05 EE15 FF14 GG09 GG10 GG14 HH09 5F033 HH04 HH28 LL04 MM07 QQ59 QQ65 QQ74 QQ75 RR15 VV06 WW03 XX14 BB14 BG14 BB14 BC01 AA00 AB03 BF04 BF11 BF18 BF32 BF33 BF38 BG08 BG12 BG28 BG30 BG32 BG34 BH15 BK02 BK13 BK20 CB01 CC07 CC12 CC19

Claims (4)

[Claims] A step of forming a polycide film via a gate oxide film on a substrate surface on which a desired element region is formed; a boron ion implantation step of ion-implanting boron or boron fluoride into the polycide film; Patterning the polycide film to form a gate electrode, and ion-implanting impurities using the gate electrode as a mask,
A method for manufacturing a semiconductor device, comprising: a step of forming a source / drain diffusion layer; a step of depositing an interlayer insulating film; and a heat treatment step of performing a heat treatment on the interlayer insulating film. 2. The method according to claim 1, wherein the heat treatment step is a high-temperature heat treatment step of maintaining the temperature at 900 ° C. or higher for a predetermined time. 3. The method according to claim 1, wherein the step of forming the source / drain region is a step of implanting N-type impurity ions. 4. The method according to claim 1, wherein the step of depositing the interlayer insulating film is a step of forming a BPSG film by vapor phase growth.