JPH02109320A - Manufacture of heteroepitaxial film - Google Patents

Manufacture of heteroepitaxial film

Info

Publication number
JPH02109320A
JPH02109320A JP26044788A JP26044788A JPH02109320A JP H02109320 A JPH02109320 A JP H02109320A JP 26044788 A JP26044788 A JP 26044788A JP 26044788 A JP26044788 A JP 26044788A JP H02109320 A JPH02109320 A JP H02109320A
Authority
JP
Japan
Prior art keywords
layer
dislocation density
grown
substrate
gaas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26044788A
Other languages
Japanese (ja)
Inventor
Koichi Ishida
石田 宏一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP26044788A priority Critical patent/JPH02109320A/en
Publication of JPH02109320A publication Critical patent/JPH02109320A/en
Pending legal-status Critical Current

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  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To provide a heteroepitaxial film having a low dislocation density using a simple method by forming a three- or four-dimensional mixed crystal buffer layer having a grating constant in the same degree as the desired epi. layer, and thereupon allowing an epi. layer to grow. CONSTITUTION:On an Si substrate an InxGa1-x-yAlyP buffer layer 2 is grown at a temp. of 560 deg.C by the use of InGa alloy. In, Al as the III group source and red phosphorus as the V group source, where x and y are determined so that the grating constant becomes in the same degree as that of GaAs. This is followed by grown of an approx. 3mum GaAs layer 3 at the same temp. This decreases the dislocation density in the epi. layer to 1/10<2>-10<3> of normal value, to enable manufacture of heteroepitaxial film with a low dislocation density by simple method.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明はへテロエピタキシャル薄膜の製造方法に関し、
ざらに詳しくは基板と大ぎく格子定数の異なる低格子欠
陥密度のへテロエピタキシャル薄膜の製造方法に関する
ものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a heteroepitaxial thin film,
More specifically, the present invention relates to a method of manufacturing a heteroepitaxial thin film having a low lattice defect density and having a lattice constant substantially different from that of a substrate.

[従来の技術] これまで基板と格子定数の大きく異なるエピタキシャル
薄膜、例えばSi基板上のGaASi膜の成長は、主G
、m M OCV D法、MBE法等1’lい、2段階
成長法と呼ばれている方法によって行われていた。この
方法では、まず低温の成長湿度で膜厚の薄いバッファ層
を成長する。このバッファ層と基板との界面にはミスフ
ィツト転位が導入され、エピタキシャル層と基板との格
子定数の相異による応力は緩和され、バッファ層の格子
は本来の格子にもどる。よってこのバッファ層の上に、
通常の高温の成長温度で容易にエピタキシャル層を成長
することができる。
[Prior Art] Until now, the growth of an epitaxial thin film with a lattice constant significantly different from that of a substrate, such as a GaASi film on a Si substrate, has been
, mMOCVD method, MBE method, etc., and a method called a two-step growth method. In this method, a thin buffer layer is first grown at low temperature and humidity. Misfit dislocations are introduced into the interface between the buffer layer and the substrate, the stress due to the difference in lattice constant between the epitaxial layer and the substrate is relaxed, and the lattice of the buffer layer returns to its original lattice. Therefore, on top of this buffer layer,
Epitaxial layers can be easily grown at normal high growth temperatures.

[発明が解決しようとする課題] しかしながら、このように成長したエピタキシャル薄膜
は、非常に多り(109〜108cm−2)の転位を有
している。この転位の一部はミスフィツト転位の端部で
あり、その他は成長中において局所的な応力の集中によ
って生じたものである。
[Problems to be Solved by the Invention] However, the epitaxial thin film grown in this manner has a very large number (109 to 108 cm-2) of dislocations. Some of these dislocations are ends of misfit dislocations, and others are caused by local stress concentration during growth.

このエピタキシャル層中の転位密度を低減化するために
、エピタキシャル層成長中に歪超格子を加えることや、
成長後に熱処理をすることなどが試みられてあり、この
ようにして種々の処理を施したエピタキシャル層におい
ては、転位密度は杓106Crn−2である。
In order to reduce the dislocation density in this epitaxial layer, a strained superlattice can be added during epitaxial layer growth,
Attempts have been made to perform heat treatment after growth, and in epitaxial layers subjected to various treatments in this way, the dislocation density is 106Crn-2.

しかし、歪超格子を1J11えたり、熱処理を施したり
することは、ヘテロエピタキシ1ノル層の製3i方法を
非常に煩唯なものにするという欠点がある。
However, increasing the strained superlattice by 1J11 or performing heat treatment has the disadvantage of making the 3i method for producing a heteroepitaxial 1-Nor layer extremely complicated.

本発明の目的は、これらの問題を解決した簡便な低乾イ
171や1度のl\テロTピタキシャル薄膜の製造方法
を提供づることにある。
It is an object of the present invention to provide a simple method for producing a low-dry film 171 and a one-time tero-T pitaxial thin film that solves these problems.

[課題を解決するための手段] 本発明は、格子定数の異なる基板上にヘテロエピタキシ
X・ル成長を行うことよりなるヘテロエピタキシャル薄
膜の製造方法において、基板上に、後に形成すべきエピ
タキシャル層と同程度の格子定数をイ”iする3元また
は4元混晶のバッフ?用を成長した後、該バッフ1薯上
に所望のエピタキシャル補を成長することを特徴と覆る
ヘテロエピタキシX・ル薄膜の製造方法である。
[Means for Solving the Problem] The present invention provides a method for manufacturing a heteroepitaxial thin film by performing heteroepitaxial X-L growth on a substrate having a different lattice constant, in which an epitaxial layer to be formed later and an epitaxial layer to be formed later are formed on the substrate. The method is to grow a ternary or quaternary mixed crystal buffer having a similar lattice constant, and then grow a desired epitaxial layer on the buffer. This is a manufacturing method.

[作用] 3元混晶のInトxGaxAsヤ、4元混晶のGa1−
8嶋As i−y py、 In1. Ga、 As 
i−y pyでは、ミスフィツト転位発生の臨界膿汁が
GaAsヤIr+Pのような2元化合物に比べて2〜3
倍人きいことが知られている(フィジカ・スティタス・
ソリデイ。
[Function] IntxGaxAs of ternary mixed crystal, Ga1- of quaternary mixed crystal
8 Shima As i-y py, In1. Ga, As
In i-y py, the critical pus for misfit dislocation generation is 2-3 compared to binary compounds such as GaAs and Ir+P.
Known to be twice as sensitive (Physica status)
solid day.

(a) 70. 277(1982):ジャーナル・オ
ブ・アプライド・フィツクス、 52.4575 (1
981) )。このことは結晶が多元混晶になるにつれ
て結晶中における降伏応力が大きくなることを示し−(
いる。つまり、このことは同一の応力がかかった場合、
多元混晶の方が転位が発生しにくくなると考えられる。
(a) 70. 277 (1982): Journal of Applied Fixtures, 52.4575 (1
981) ). This indicates that the yield stress in the crystal increases as the crystal becomes a multicomponent mixed crystal.
There is. In other words, this means that if the same stress is applied,
It is thought that dislocations are less likely to occur in multi-component mixed crystals.

従って多元混晶のバッファ層を用いることにより、バッ
ファ図中に発生する転位密度を低減することができ、そ
の上に成長するエピタキシャル層に対し、上方に伝播す
る転位密度を■げることができる。
Therefore, by using a multi-component mixed crystal buffer layer, it is possible to reduce the dislocation density that occurs in the buffer diagram, and it is possible to reduce the dislocation density that propagates upward to the epitaxial layer that grows on it. .

[実施例] 次に、本発明の実施例について、図面を参照して詳細に
説明する。
[Example] Next, an example of the present invention will be described in detail with reference to the drawings.

本実施例においては、InxGa1−x−ρV、 Pを
バッファ Qと1−るGaAsのSi上の成長について
説明する。第1図は本実施例によってjqられたヘテロ
エピつキシ(・ル層のN略断面図を示したものである。
In this example, growth of GaAs on Si where InxGa1-x-ρV, P is a buffer Q and 1- will be described. FIG. 1 shows a schematic cross-sectional view of the heteroepithelial layer formed according to this embodiment.

十ビタキシャル1璋嗅の成長はMBFによって行った。Decabitaxial growth was performed by MBF.

まず31塁板1表面を石板らの方法(コレクティブ1−
゛・ペーパーズ・オ/φエム・ヒー・イー/シー・ニス
・i−イー/” 2 +東京、 1982. 183ペ
ージ参照)により清浄化した。次に基板温度を560℃
にし、■族源としてはI I’l G a合金と、In
とMの金属を用い、VK源としては赤燐を用いて、In
xGa1−x−、H町Pバッファ層2を成長した。x、
 yの組成は予めcaAs上に成長させて、Δa/aが
1X10−3より小さくなるように確かめた値であり、
本実施例ではx=0.47. y=0.11とした。な
あ、aはGaAsの格子定数であり、△aはGaAsと
InxGa1−x−VM、 Pの格子定数の差である。
First, the first surface of the 31st base plate was prepared using the method of Ishiita et al. (collective 1-
The substrate temperature was then increased to 560°C.
The group ■ sources include I I'l Ga alloy and In
and M metals, red phosphorus is used as the VK source, and In
xGa1-x-, H town P buffer layer 2 was grown. x,
The composition of y is a value grown on caAs in advance and confirmed that Δa/a is smaller than 1X10-3,
In this example, x=0.47. y=0.11. Note that a is the lattice constant of GaAs, and Δa is the difference in the lattice constants of GaAs and InxGa1-x-VM,P.

0.Qm/hの成長gmで約2000人のInxGa1
−x、 M、 Pバッファ祠2を成長した。次に同温度
で約3μsのGaAs層3を成長した。
0. Approximately 2000 InxGa1 with growth gm of Qm/h
-x, M, P buffer shrine 2 was grown. Next, a GaAs layer 3 was grown for about 3 μs at the same temperature.

このように成長したGaAS層30層面0表面0°Cで
20秒間、溶融KOHでエツチングし、GaAS層表面
の転位密度を評価したところ、10Cm’−2であった
The surface of the GaAS layer 30 grown in this manner was etched with molten KOH at 0° C. for 20 seconds, and the dislocation density on the surface of the GaAS layer was evaluated and found to be 10 Cm'-2.

この値は、GaASを通常の2段階成長法により、直接
Si基板上に成長したときに比べ、2〜3桁の減少であ
った。この結果は、InxGaト、−yMVPバッフ1
唐内の転位密度か減少したことによると考えることがで
きる。
This value was 2 to 3 orders of magnitude lower than when GaAS was grown directly on a Si substrate by a normal two-step growth method. This result shows that InxGato, -yMVP buffer 1
This can be thought to be due to a decrease in the dislocation density within the Karanai region.

[発明の効果1 以上説明したように、本発明の方法によって作製したエ
ピタキシャル層中の転位密度は、通常の方法に比べて1
0”〜103分の1に減少しており、また従来のように
歪超格子を加えたり、熱処理を施したりすることなく、
低転位密度のへテロエごタキシセル膜を簡便な方法で製
造することができる。
[Effect of the invention 1 As explained above, the dislocation density in the epitaxial layer produced by the method of the present invention is 1
0" to 1/103, and without adding a strained superlattice or heat treatment as in conventional methods,
A heterotaxy cell film with a low dislocation density can be manufactured by a simple method.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明の一実施例によって得られるヘテロエ
ピタキシャル層の概略断面図である。 1・・・Si基板 2・・In、 Ga1−x−yMy 3・・・GaA3層 バッファ層 代 理 人
FIG. 1 is a schematic cross-sectional view of a heteroepitaxial layer obtained according to an embodiment of the present invention. 1...Si substrate 2...In, Ga1-x-yMy 3...GaA three-layer buffer layer agent

Claims (1)

【特許請求の範囲】[Claims] (1)格子定数の異なる基板上にヘテロエピタキシャル
成長を行うことよりなるヘテロエピタキシャル薄膜の製
造方法において、基板上に、後に形成すべきエピタキシ
ャル層と同程度の格子定数を有する3元または4元混晶
のバッファ層を成長した後、該バッファ層上に所望のエ
ピタキシャル層を成長することを特徴とするヘテロエピ
タキシャル薄膜の製造方法。
(1) In a method for manufacturing a heteroepitaxial thin film that involves performing heteroepitaxial growth on a substrate with a different lattice constant, a ternary or quaternary mixed crystal having a lattice constant comparable to that of an epitaxial layer to be formed later is formed on the substrate. 1. A method for producing a heteroepitaxial thin film, which comprises growing a buffer layer and then growing a desired epitaxial layer on the buffer layer.
JP26044788A 1988-10-18 1988-10-18 Manufacture of heteroepitaxial film Pending JPH02109320A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26044788A JPH02109320A (en) 1988-10-18 1988-10-18 Manufacture of heteroepitaxial film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26044788A JPH02109320A (en) 1988-10-18 1988-10-18 Manufacture of heteroepitaxial film

Publications (1)

Publication Number Publication Date
JPH02109320A true JPH02109320A (en) 1990-04-23

Family

ID=17348063

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26044788A Pending JPH02109320A (en) 1988-10-18 1988-10-18 Manufacture of heteroepitaxial film

Country Status (1)

Country Link
JP (1) JPH02109320A (en)

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