JPH02177320A - Manufacture of hetero epitaxial thin film - Google Patents

Manufacture of hetero epitaxial thin film

Info

Publication number
JPH02177320A
JPH02177320A JP25697088A JP25697088A JPH02177320A JP H02177320 A JPH02177320 A JP H02177320A JP 25697088 A JP25697088 A JP 25697088A JP 25697088 A JP25697088 A JP 25697088A JP H02177320 A JPH02177320 A JP H02177320A
Authority
JP
Japan
Prior art keywords
layer
substrate
thin film
buffer layer
grown
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25697088A
Other languages
Japanese (ja)
Inventor
Koichi Ishida
石田 宏一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP25697088A priority Critical patent/JPH02177320A/en
Publication of JPH02177320A publication Critical patent/JPH02177320A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a hetero epitaxial film of low transition density by a simple method by growing a buffer layer, to which n-type or amphoteric impurity high concentration is added, on a substrate, and then growing a desired epitaxial layer on the buffer layer. CONSTITUTION:First, the surface of an Si substrate 1 is cleaned. Next, a buffer layer, to which n-type or amphoteric impurity in concentration of 10<18>cm<-3> or more is added, for example, GaAs buffer layer 2, to which In is added by 2X10<19>cm<-3>, is grown on this substrate 1. Next, a desired epitaxial layer, for example, a GaAs layer 3 is grown on the layer 2. Hereby, a hetero epitaxial film of low transition density can be made without adding distorted superlattice or applying heat treatment.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明はへテロエごタキシャル薄膜の製造方法に関し、
ざらに詳しくは基板と大きく格子定数の異なる低格子欠
陥密度のへテロエピタキシャル薄膜の製造方法に関する
ものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a heterogeneous taxial thin film.
More specifically, the present invention relates to a method for manufacturing a heteroepitaxial thin film having a low lattice defect density and having a lattice constant significantly different from that of a substrate.

[従来の技術] これまで基板と格子定数の人ぎく異なるエピタキシャル
簿膜、例えば81基板上のGaAs薄膜の成長は、主G
、: M OCV D法、MBE法等ヲff1(、N、
2段階成長法と呼ばれている方法によって行われている
。この方法では、まず低温の成長温度で膜厚の薄いバッ
ファ層を成長する。このバッファ層と基板との界面には
ミスフィツト転位が尋人され、エピタキシャル層と基板
との格子定数の相異による応力は緩和され、バッフ7層
の格子は本来の格子にもどる。よってこのバッファ層の
上に、通常の高温の成長温度で容易にエピタキシャル層
を成長することができる。
[Prior Art] Until now, the growth of a GaAs thin film on an epitaxial film with a lattice constant significantly different from that of the substrate, for example, a 81-substrate, has been
, : MOCV D method, MBE method etc. ff1(,N,
This is done using a method called the two-step growth method. In this method, a thin buffer layer is first grown at a low growth temperature. Misfit dislocations are generated at the interface between the buffer layer and the substrate, the stress due to the difference in lattice constant between the epitaxial layer and the substrate is relaxed, and the lattice of the buffer layer 7 returns to its original lattice. Therefore, an epitaxial layer can be easily grown on this buffer layer at a normal high temperature growth temperature.

〔発明が解決しようとする課題] しかしながら、このように成長したエピタキシャル薄膜
は、非常に多り(109〜108.−2 )の転位を有
している。このエピタキシャル層t層中の転位密度を低
減するために、エピタキシャル層成長中に歪超格子を加
えることや、成長後に熱処理をすることなどが試みられ
ており、このように種々の処理を施したエピタキシt・
ル層においては、転位密度は約106cm−2である。
[Problems to be Solved by the Invention] However, the epitaxial thin film grown in this manner has a very large number (109 to 108.-2) of dislocations. In order to reduce the dislocation density in this epitaxial T-layer, attempts have been made to add a strained superlattice during epitaxial layer growth and to perform heat treatment after growth. Epitaxy
In the Le layer, the dislocation density is about 106 cm-2.

しかし、歪超格子を加えたり、熱処理を施したりするこ
とは、ヘテロエピタキシャル層の製造方法を非常に煩雑
なものにするという欠点がある。
However, adding a strained superlattice or performing heat treatment has the drawback of making the method for manufacturing the heteroepitaxial layer extremely complicated.

本発明の目的は、これらの問題を解決した簡便な低転位
密度のへテロエピタキシャル薄膜の製造方法を提供する
ことにある。
An object of the present invention is to provide a simple method for manufacturing a heteroepitaxial thin film with a low dislocation density, which solves these problems.

[課題を解決するための手段] 本発明は、格子定数の異なる基板上にヘテロエピタキシ
ャル成長を行うことよりなるヘテロエピタキシャルM膜
の製造方法において、基板上に1018cm−3以上の
濃度のn型または両性不純物を添加したバッファ層を成
長した後、該バッファ層上に所望のエピタキシャル層を
成長することを特徴とづるヘテロエピタキシX/層薄膜
の製造方法である。
[Means for Solving the Problems] The present invention provides a method for manufacturing a heteroepitaxial M film, which comprises performing heteroepitaxial growth on a substrate having a different lattice constant. This is a method for producing a heteroepitaxy X/layer thin film, which comprises growing a buffer layer doped with impurities and then growing a desired epitaxial layer on the buffer layer.

[作用] GaAsエピタキシャル層と基板の間に発生するミスフ
ィツト転位のほとんどは、基板が(100)面の場合、
バーガースベクトルが面に平行なa/2< 110>の
純粋刃状転位である。一方、エピタキシャル層中の転位
のバーガースベクトルは、GaASの格子定数をaとす
ると、a/2<110>のものと(m)面に乗っている
a/2<011>のちのとがある。従って、バーガース
ベクトルがa/2<110>の転位は短スフイツト転位
の端部がエピタキシャル層上部につきぬけている部分に
対応していると考えられる。一方、バーガースベタ1〜
ルがa/2<011>の転位は、すべり転位であり、そ
の多くはエピタキシャル層成長中に局所的な応力集中に
より生じたと考えられる。
[Function] Most of the misfit dislocations that occur between the GaAs epitaxial layer and the substrate occur when the substrate is in the (100) plane.
It is a pure edge dislocation with Burgers vector parallel to the plane a/2<110>. On the other hand, when the lattice constant of GaAS is a, the Burgers vectors of dislocations in the epitaxial layer include those of a/2<110> and those of a/2<011> lying on the (m) plane. Therefore, it is considered that the dislocation where the Burgers vector is a/2<110> corresponds to the portion where the end of the short Swift dislocation penetrates into the upper part of the epitaxial layer. On the other hand, Burgers Betta 1~
Dislocations with a le of a/2<011> are slip dislocations, and most of them are considered to have occurred due to local stress concentration during epitaxial layer growth.

よって、バッフ7層の結晶の降伏応力を大きくすること
ができれば、即ら、転位を発生しにくくすることができ
れば、少なくとも、バーガースベクトルがa/2<01
1>のすべり転位の発生はかなり抑制できると考えられ
る。GaA’Sの降伏応力を大きくする方法はずでにバ
ルク結晶の成長において、n型不純物や、Inのような
アイソエレクトロニック不純物原子を1018cm−3
以上の高温度に添加することによって実現できることが
知られている(ジャーナル・オブ・アプライド・フィツ
クス。
Therefore, if the yield stress of the crystal in the buff 7 layer can be increased, that is, if dislocations can be made less likely to occur, then at least the Burgers vector will be a/2<01
It is considered that the occurrence of slip dislocations of 1> can be considerably suppressed. A method to increase the yield stress of GaA'S is to increase the yield stress of GaA'S by adding n-type impurity atoms or isoelectronic impurity atoms such as In to 1018 cm-3 during bulk crystal growth.
It is known that this can be achieved by adding it to a high temperature (Journal of Applied Fixtures).

、19. 822(1978) )。よって、同様の方
法をエピタキシャル層のバッファ層の成長に適用すれば
、バッファ層中の転位密度を低減し、さらには、その上
に成長するエピタキシャル層中を上方に伝播する転位の
密度を下げることができる。
, 19. 822 (1978)). Therefore, if a similar method is applied to the growth of a buffer layer in an epitaxial layer, the dislocation density in the buffer layer can be reduced, and furthermore, the density of dislocations propagating upward in the epitaxial layer grown on it can be reduced. Can be done.

[実施例] 次に本発明の実施例について、図面を参照して詳細に説
明する。
[Example] Next, an example of the present invention will be described in detail with reference to the drawings.

本実施例においては、Si基板上にGaAs1膜をMO
CVD法によって成長する方法について説明する。
In this example, a GaAs1 film is formed on a Si substrate using an MO
A method of growing by CVD method will be explained.

第1図は本実施例によって得られたヘテロエピタキシャ
ル層の概略断面図でおる。まず、Si基板1を1000
℃の水素で希釈したアルシン中に2分間置くことにより
、その表面を清浄化した。
FIG. 1 is a schematic cross-sectional view of the heteroepitaxial layer obtained in this example. First, Si substrate 1 is
The surface was cleaned by placing it in arsine diluted with hydrogen at 0C for 2 minutes.

次に基板温度を420℃にし、Ga (C113) 3
、In (Cf13) 3、Ast13を原料とし、I
nを2 X 1019cm’添加した膜厚100人のG
aAsバッファM2を成長した。次に基板温度を750
℃にし、膜厚2tIInのGaAs層3を成長した。
Next, the substrate temperature was set to 420°C, and Ga (C113) 3
, In (Cf13) 3, using Ast13 as raw material, I
2 x 1019 cm' of film thickness 100 G
AAs buffer M2 was grown. Next, increase the substrate temperature to 750
℃, and a GaAs layer 3 having a thickness of 2tIIn was grown.

このように成長したGaAs層3の表面を、360℃で
20秒間、溶融KOHでエツチングしたところ、転位密
度は106Ctn−2であった。
When the surface of the GaAs layer 3 thus grown was etched with molten KOH at 360 DEG C. for 20 seconds, the dislocation density was found to be 106 Ctn-2.

なお、本実施例においてはエピタキシャル薄膜としてG
aAsを例にとって説明したが、このほか、InP等の
種々のエピタキシャル薄膜の製造に適用することができ
る。
Note that in this example, G was used as the epitaxial thin film.
Although the description has been made using aAs as an example, the present invention can also be applied to the production of various epitaxial thin films such as InP.

[発明の効果1 以上説明したように、本発明の方法によって作製したエ
ピタキシャル層中の転位密度は、通常の方法に比べて1
02〜103分の1に減少しており、また従来のように
歪超格子を加えたり、熱処理を施したりすることなく、
低転位密度のへテロエピタキシャル膜を簡便な方法で製
造することができる。
[Effect of the invention 1 As explained above, the dislocation density in the epitaxial layer produced by the method of the present invention is 1
It has been reduced to 1/02 to 103 times, and without adding a strained superlattice or heat treatment as in the past,
A heteroepitaxial film with a low dislocation density can be manufactured by a simple method.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の一実施例によって17られるヘテロ
エピタキシャル層の概略断面図である。 1・・・Si基板 2・・・GaASバッファ層 3・・・GaAs層
FIG. 1 is a schematic cross-sectional view of a heteroepitaxial layer 17 according to one embodiment of the present invention. 1...Si substrate 2...GaAS buffer layer 3...GaAs layer

Claims (1)

【特許請求の範囲】[Claims] (1)格子定数の異なる基板上にヘテロエピタキシャル
成長を行うことよりなるヘテロエピタキシャル薄膜の製
造方法において、基板上に10^1^8cm^−^3以
上の濃度のn型または両性不純物を添加したバッファ層
を成長した後、該バッファ層上に所望のエピタキシャル
層を成長することを特徴とするヘテロエピタキシャル薄
膜の製造方法。
(1) In a method for manufacturing a heteroepitaxial thin film that involves performing heteroepitaxial growth on a substrate with a different lattice constant, a buffer doped with n-type or amphoteric impurities at a concentration of 10^1^8 cm^-^3 or more is added on the substrate. 1. A method for producing a heteroepitaxial thin film, which comprises growing a desired epitaxial layer on the buffer layer after growing the layer.
JP25697088A 1988-10-14 1988-10-14 Manufacture of hetero epitaxial thin film Pending JPH02177320A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25697088A JPH02177320A (en) 1988-10-14 1988-10-14 Manufacture of hetero epitaxial thin film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25697088A JPH02177320A (en) 1988-10-14 1988-10-14 Manufacture of hetero epitaxial thin film

Publications (1)

Publication Number Publication Date
JPH02177320A true JPH02177320A (en) 1990-07-10

Family

ID=17299901

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25697088A Pending JPH02177320A (en) 1988-10-14 1988-10-14 Manufacture of hetero epitaxial thin film

Country Status (1)

Country Link
JP (1) JPH02177320A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014022564A (en) * 2012-07-18 2014-02-03 Asahi Kasei Corp Compound semiconductor substrate and manufacturing method therefor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014022564A (en) * 2012-07-18 2014-02-03 Asahi Kasei Corp Compound semiconductor substrate and manufacturing method therefor

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