JPH0210751A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0210751A JPH0210751A JP16232288A JP16232288A JPH0210751A JP H0210751 A JPH0210751 A JP H0210751A JP 16232288 A JP16232288 A JP 16232288A JP 16232288 A JP16232288 A JP 16232288A JP H0210751 A JPH0210751 A JP H0210751A
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- wiring pattern
- semiconductor element
- electrically insulating
- insulating substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052802 copper Inorganic materials 0.000 abstract description 3
- 239000010949 copper Substances 0.000 abstract description 3
- 239000000463 material Substances 0.000 abstract description 3
- 238000007747 plating Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- OINMNSFDYTYXEQ-UHFFFAOYSA-M 2-bromoethyl(trimethyl)azanium;bromide Chemical compound [Br-].C[N+](C)(C)CCBr OINMNSFDYTYXEQ-UHFFFAOYSA-M 0.000 description 1
- 239000012778 molding material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野コ
本発明は、半導体装置、プラスチックピングリッドアレ
ー（以下ＰＰＧＡと称す）の構造に関す［発明の概要コ
本発明は、ＰＰＧＡの構造において、半導体素子と配線
パターンとをギヤングボンディングで接続する事により
、高密度、多ピンのボンディングを実現し、且短時間で
接続できる様にしたものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a structure of a semiconductor device, a plastic pin grid array (hereinafter referred to as PPGA). By connecting the element and the wiring pattern using gigantic bonding, high-density, multi-pin bonding is realized, and the connection can be made in a short time.
［従来の技術］
従来のＰＰＧＡのボンディングは、特開昭６２−９２３
４５．特開昭６２−９８６４７．特開昭６２−１４１７
４５に記載され第２図で示す様に半導体素子２１の、配
線パターン２２との接続は、ボンディングワイヤー２６
を用いたワイヤーボンディングで行なわれていた。リー
ドピン２４は、配線パターン２２と電気的に接続され、
電気絶縁基板２５に垂直に設けられている。ワイヤーボ
ンディングの後、モールド材２６でモールド、及びリッ
ド２７を接着し、パッケージの組立を行なっていた。[Prior art] Conventional PPGA bonding is disclosed in Japanese Patent Application Laid-Open No. 62-923.
45. Japanese Patent Publication No. 62-98647. Japanese Patent Publication No. 1417/1986
As described in 45 and shown in FIG.
This was done using wire bonding. The lead pin 24 is electrically connected to the wiring pattern 22,
It is provided perpendicularly to the electrically insulating substrate 25. After wire bonding, the mold and lid 27 were bonded together using a molding material 26 to assemble the package.
［発明が解決しようとする課題］
しかし、前述の技術では、絶縁基板は、リードピンのピ
ッチを、２．５４ｒａｎ又は１．２７ ｒｒａにして、
多数設ければ、４００ビン程度の基板を作る事は可能で
あったが、その様な半導体素子をワイヤーポンディング
で実装する場合、アルミパッドのピッチは１５０μｍ程
度必要となる為、半導体素子のサイズは１５酎０程度に
なりパターンの微細化に伴なうチップサイズの縮小化に
もかかわらず１５ｍ０よりも小さな半導体素子は実装で
きなかった。[Problems to be Solved by the Invention] However, in the above-mentioned technique, the pitch of the lead pins of the insulating substrate is set to 2.54 ran or 1.27 rra,
It was possible to make a board with about 400 bins if a large number of them were installed, but when mounting such a semiconductor element by wire bonding, the pitch of the aluminum pads would be about 150 μm, so the size of the semiconductor element is approximately 15m0, and despite the reduction in chip size due to miniaturization of patterns, semiconductor elements smaller than 15m0 could not be mounted.
又、これに対応する配線パターンは、ワイヤーボンディ
ング部の配線パターンのピッチが０．２ｍ＋ｎ程度にな
り、基板製作の歩留が極めて低かった。Further, in the wiring pattern corresponding to this, the pitch of the wiring pattern in the wire bonding part was about 0.2 m+n, and the yield of manufacturing the board was extremely low.
さらに、多ピンのボンディングをワイヤーボンディング
で行なう事は大変時間を要した。Furthermore, bonding multiple pins using wire bonding takes a lot of time.
そこで本発明はこの様な問題点を解決するものでその目
的とするところは、１０ｍｍ０程度の半導体素子を４０
０ピン程度のＰＰＧＡに実装する方法を、基板製作の歩
留りを下げず、且、ボンディングの工数をかけずに提供
する事にある。Therefore, the present invention is intended to solve such problems, and its purpose is to make a semiconductor element of about 10mm0 into a 40mm
The purpose of the present invention is to provide a method for mounting on a PPGA with about 0 pins without lowering the yield of manufacturing the board and without requiring the number of bonding steps.
〔課題を解決する為の手段］
本発明の半導体装置は、リードピンを電気的絶縁基板に
垂直に多数設けたＰＰＧＡにおいて、該リードピンと電
気的に接続している前記電気的絶縁基板上の配線パター
ンが、半導体素子と、ギヤングボンディングで接続して
いる事を特徴とする［実施例］
第１図は本発明の実施例である。半導体素子２１に形成
されたバンプ１１と表面にメツキを施された銅フィンガ
ー１２はギヤングボンディングで接続されている。リー
ドピン２４は、配線パターン２２と電気的に接続され電
気絶縁基板２５に垂直に設けられている。ギヤングボン
ディングの後、モールド材２６でモールド及びリッド２
７を接着し、パッケージの組立を行なっている。[Means for Solving the Problems] A semiconductor device of the present invention is a PPGA in which a large number of lead pins are vertically provided on an electrically insulating substrate, and a wiring pattern on the electrically insulating substrate electrically connected to the lead pins. [Embodiment] FIG. 1 shows an embodiment of the present invention. The bumps 11 formed on the semiconductor element 21 and the copper fingers 12 whose surfaces are plated are connected by gigantic bonding. The lead pin 24 is electrically connected to the wiring pattern 22 and provided perpendicularly to the electrically insulating substrate 25 . After gigantic bonding, mold and lid 2 are molded with mold material 26.
7 is glued together and the package is assembled.
第３図は本発明の他の実施例で、ＢＴＡＢ方式、すなわ
ち半導体素子の電極はアルミパッドのままで、フィンガ
ー１２に突起１３をつけ、ギヤングボンディングする方
式である。FIG. 3 shows another embodiment of the present invention, which is a BTAB method, in which the electrodes of the semiconductor element remain aluminum pads, projections 13 are attached to the fingers 12, and gigantic bonding is performed.
［発明の効果］
以上の様に本発明によれば、ＰＰＧＡの配線パ声−ンと
、半導体素子をギヤングボンディングで接続する事によ
り４００ビンＰＰＧＡでワイヤーポンディングではチッ
プサイズが小さすぎて実装不可能な１０閣０程度のチッ
プでも実装可能となる。さらに、それらが基板の歩留り
も下げる事なく、ボンディングの工数もかけずにできる
という効果を有する。[Effects of the Invention] As described above, according to the present invention, by connecting the PPGA wiring pattern and the semiconductor element by giant bonding, the chip size is too small to be mounted using wire bonding in a 400-bin PPGA. It becomes possible to implement even an impossible chip with a size of about 1000. Furthermore, they have the advantage that they can be performed without lowering the yield of substrates and without requiring any man-hours for bonding.
第１図は、本発明の半導体装置の一実施例を示す断面図
。
第２図は、従来の半導体装置の実施例を示す断面図。
第６図は、本発明の他の実施例を示す断面図。
１・・・・・・・・・バンプ
２・・・・・・・・・銅フィンガー
３・・・・・・・・・フィンガーにつけた突起４・・・
・・・・・・リードピン
５・・・・・・・・・絶縁基板
６・・・・・・・・・モールド材
７ ・・・ ・・・ ・・・ リ ッ ド以上FIG. 1 is a sectional view showing an embodiment of a semiconductor device of the present invention. FIG. 2 is a sectional view showing an example of a conventional semiconductor device. FIG. 6 is a sectional view showing another embodiment of the present invention. 1...Bump 2...Copper finger 3...Protrusion attached to the finger 4...
・・・・・・Lead pin 5・・・・・・・・・Insulating board 6・・・・・・Mold material 7 ・・・・・・・・・ More than lid
Claims (1)
ックピングリッドアレーにおいて、該リードピンと電気
的に接続している前記電気絶縁基板上の配線パターンが
、半導体素子と、ギャングボンディングで接続されてい
る事を特徴とする半導体装置。In a plastic pin grid array in which a large number of lead pins are provided perpendicularly to an electrically insulating substrate, a wiring pattern on the electrically insulating substrate that is electrically connected to the lead pins is connected to a semiconductor element by gang bonding. Characteristic semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16232288A JPH0210751A (en) | 1988-06-28 | 1988-06-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16232288A JPH0210751A (en) | 1988-06-28 | 1988-06-28 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0210751A true JPH0210751A (en) | 1990-01-16 |
Family
ID=15752330
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16232288A Pending JPH0210751A (en) | 1988-06-28 | 1988-06-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0210751A (en) |
-
1988
- 1988-06-28 JP JP16232288A patent/JPH0210751A/en active Pending
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