JPH02106959A - Manufacture of semiconductor memory - Google Patents
Manufacture of semiconductor memoryInfo
- Publication number
- JPH02106959A JPH02106959A JP63260833A JP26083388A JPH02106959A JP H02106959 A JPH02106959 A JP H02106959A JP 63260833 A JP63260833 A JP 63260833A JP 26083388 A JP26083388 A JP 26083388A JP H02106959 A JPH02106959 A JP H02106959A
- Authority
- JP
- Japan
- Prior art keywords
- film
- conductive layer
- oxygen
- silicon nitride
- trichloroethane
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910001882 dioxygen Inorganic materials 0.000 claims abstract description 5
- 239000007789 gas Substances 0.000 claims abstract description 5
- 230000015654 memory Effects 0.000 claims description 17
- 239000010410 layer Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 8
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000002344 surface layer Substances 0.000 claims 1
- 239000001301 oxygen Substances 0.000 abstract description 11
- 229910052760 oxygen Inorganic materials 0.000 abstract description 11
- UOCLXMDMGBRAIB-UHFFFAOYSA-N 1,1,1-trichloroethane Chemical compound CC(Cl)(Cl)Cl UOCLXMDMGBRAIB-UHFFFAOYSA-N 0.000 abstract description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 10
- 239000003990 capacitor Substances 0.000 abstract description 9
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 5
- 238000002955 isolation Methods 0.000 abstract description 5
- 230000003647 oxidation Effects 0.000 abstract description 4
- 238000007254 oxidation reaction Methods 0.000 abstract description 4
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 abstract description 3
- 229910001385 heavy metal Inorganic materials 0.000 abstract description 3
- 150000002500 ions Chemical class 0.000 abstract description 3
- 229910052708 sodium Inorganic materials 0.000 abstract description 3
- 239000011734 sodium Substances 0.000 abstract description 3
- 230000010354 integration Effects 0.000 abstract description 2
- 238000005247 gettering Methods 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 238000001312 dry etching Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体メモリーのメモリーセルの製造方法に
関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a memory cell of a semiconductor memory.
従来の技術
近年、半導体産業の急速な発展に伴い、半導体メモリー
に対し、高集積化、大容量化が要求されている。その為
特に半導体メモリーの主要素であるメモリーセルの高密
度化が必須となる。一方、大容量化の而では、電荷蓄積
部の絶縁膜の薄膜化。2. Description of the Related Art In recent years, with the rapid development of the semiconductor industry, there has been a demand for higher integration and larger capacity for semiconductor memories. Therefore, it is essential to increase the density of memory cells, which are the main element of semiconductor memory. On the other hand, in order to increase the capacity, the insulating film in the charge storage area must be made thinner.
大面積化が必要である。さらに、これらに伴い品質確保
、つまり、信頼性向上による品質の確保が要求されてい
る。その為、従来のシリコン酸化膜単層で構成されてい
た電荷蓄積部の絶縁膜にかえてシリコン窒化膜とその上
部を酸化して形成される酸化膜とからなる２層構造膜（
以下０／Ｎ膜と略す）がそれらの要求を満足するものと
して提案されている。Larger area is required. Furthermore, along with these, it is required to ensure quality, that is, to ensure quality by improving reliability. Therefore, instead of the conventional insulating film of the charge storage part consisting of a single layer of silicon oxide film, a two-layer structure film consisting of a silicon nitride film and an oxide film formed by oxidizing the upper part
A film (hereinafter abbreviated as 0/N film) has been proposed as one that satisfies these requirements.
以下に半導体メモリーのメモリーセルの電荷蓄積部（以
下メモリーセルキャパシタと略す）の絶縁膜としてＯ／
Ｎ膜を利用した場合の製造方法を述べる。Below, O/
A manufacturing method using an N film will be described.
まず、シリコン基板に素子分離絶縁膜を形成した後、第
１の導電層を形成し、さらにフォトリソグラフィー技術
とドライエツチング技術によりパターン形成を行なう。First, an element isolation insulating film is formed on a silicon substrate, a first conductive layer is formed, and a pattern is formed by photolithography and dry etching.
次に第１の導電層上にシリコン窒化膜を形成し、これを
９００ ’Ｃ前後の酸素ガス雰囲気中で酸化してＯ／Ｎ
膜を形成する。更にその上に第２の導電層を形成しメモ
リーセルキャパンタを形成する。Next, a silicon nitride film is formed on the first conductive layer, and this is oxidized in an oxygen gas atmosphere at around 900'C to O/N.
Forms a film. Further, a second conductive layer is formed thereon to form a memory cell capantor.
発明が解決しようとする課題
しかしながら、上記従来の方法では半導体メモリーのメ
モリーセルの高密度化に伴ってメモリーセルキャパシタ
の絶縁膜、すなわち、Ｏ／Ｎ膜に課せられる薄膜化、大
面積化を実現するだめの良質な膜、高信頼性の膜を確保
することが困難であった。Problems to be Solved by the Invention However, with the above conventional methods, as the density of memory cells in semiconductor memories increases, the insulating film of the memory cell capacitor, that is, the O/N film, has to be made thinner and larger in area. It has been difficult to secure high-quality and highly reliable membranes.
本発明は上記従来の問題点を解決するもので、半導体メ
モリーのメモリーセルキャパシタにおける絶縁ｌ模の信
頼性を向上させ、より高集積化された大容量の半導体メ
モリーの製造方法を提供することを目的とする。The present invention solves the above-mentioned conventional problems, and aims to improve the reliability of the insulation layer in the memory cell capacitor of a semiconductor memory, and to provide a method for manufacturing a highly integrated, large-capacity semiconductor memory. purpose.
課題を解決するだめの手段
この目的を達成する為に、本発明の半導体メモノーの製
造方法は、メモリーセルキャパシタの０／Ｎｐ形成時に
、シリコン窒化膜をトリクロロ系ガスを含む酸素ガス雰
囲気で酸化することを特徴としている。Means for Solving the Problem In order to achieve this object, the method for manufacturing a semiconductor memo of the present invention oxidizes a silicon nitride film in an oxygen gas atmosphere containing trichloro gas when forming 0/Np of a memory cell capacitor. It is characterized by
作用
この方法によれば、シリコン窒化膜の酸化時にトリクロ
ロ系ガスと酸素との反応によシ、塩素ガスと水蒸気が発
生し、酸化速度の増大および塩素ガスによるナトリウム
や重金属等の正イオンのゲッター効果等が奏され、２層
膜の膜質の向上（絶縁耐圧向上、寿命向上環）が確保で
きる。すなわち、メモリーセルキャパシタの絶縁膜であ
るＯ／Ｎ膜の高信頼性が確保できる。Effect: According to this method, chlorine gas and water vapor are generated due to the reaction between trichloro gas and oxygen during oxidation of the silicon nitride film, increasing the oxidation rate and causing the chlorine gas to become a getter of positive ions such as sodium and heavy metals. Effects etc. can be achieved, and the film quality of the two-layer film can be improved (improved dielectric strength and life span). That is, high reliability of the O/N film, which is the insulating film of the memory cell capacitor, can be ensured.
実施例
第１図は本発明の半導体メモリーの製造方法の一実施例
を示すものであり、ダイナミックランダムアクセスメモ
リー（以下ＤＲＡＭと略す）のうちメモリーセルキャパ
シタをスタック型としている場合を示す。Embodiment FIG. 1 shows an embodiment of the method for manufacturing a semiconductor memory according to the present invention, and shows a dynamic random access memory (hereinafter abbreviated as DRAM) in which the memory cell capacitors are of a stacked type.
図において、１はシリコン基板、２は素子分離絶縁膜、
３は第１の導電膜、４はシリコン窒化膜、６はシリコン
酸化膜、６はシリコン窒化膜４とシリコン酸化膜５とか
らなるＯ／Ｎ膜、７は第２の導電膜である。In the figure, 1 is a silicon substrate, 2 is an element isolation insulating film,
3 is a first conductive film, 4 is a silicon nitride film, 6 is a silicon oxide film, 6 is an O/N film consisting of silicon nitride film 4 and silicon oxide film 5, and 7 is a second conductive film.
以下に本実施例の半導体メモリーの製造方法を工程順に
説明する。The method for manufacturing the semiconductor memory of this embodiment will be explained below in order of steps.
まず、シリコン基板１上に素子分離絶縁膜２を形成する
（第１図（ａ））。次に、第１の導電層３を形成し、フ
ォトリソグラフィー技術とドライエツチング技術により
パターン形成をする（第１図（ｂ））。First, an element isolation insulating film 2 is formed on a silicon substrate 1 (FIG. 1(a)). Next, a first conductive layer 3 is formed and patterned by photolithography and dry etching (FIG. 1(b)).
そして、第１の導電層３の上にシリコン窒化膜４を形成
し、次にシリコン窒化膜４の上部をトリクロロ系ガスと
してトリクロロエタンを対酸素流量比０．９５〜２．０
０％含む酸素ガス雰囲気中で酸化し、シリコン酸化膜６
を形成し、Ｏ／Ｎ膜６とする（第１図（Ｃ））。最後に
第２の導電層７をＯ／ＮＨｅの上に形成し、メモリーセ
ルキャパシタを形成する（第１図（ｄ））。Then, a silicon nitride film 4 is formed on the first conductive layer 3, and then the upper part of the silicon nitride film 4 is filled with trichloroethane as a trichloro-based gas at a flow rate ratio of 0.95 to 2.0 to oxygen.
A silicon oxide film 6 is oxidized in an oxygen gas atmosphere containing 0%
is formed to form an O/N film 6 (FIG. 1(C)). Finally, a second conductive layer 7 is formed on the O/NHe to form a memory cell capacitor (FIG. 1(d)).
以上のように本実施例によれば、半導体メモリーのメモ
リーセルキャパシタ形成において、トリクロロエタンを
含む酸素雰囲気中でＯ／Ｎ膜６を形成させるとトリクロ
ロエタンが酸素と反応し、塩素ガスと水蒸気を発生し、
酸化速度が速くなり、また、塩素ガスによるナトリウム
や重金属等の正イオンのゲッター効果等により、０／Ｎ
膜６の信頼性を向上させることができ、高集積化された
、大容量の半導体メモリーを実現できる。また、トリク
ロロエタンは取扱い上安全であるという効果がある。尚
、上記製造方法は本発明の一実施例であり、スタック型
メモリーセルをもつＤＲＡＭに限らすトレンチ型や他の
半導体メモリーにも適用可能である。また、絶縁膜はＯ
／Ｎ膜に限定されるものでなく、０７Ｎ／Ｄ膜等の更に
多層化した膜であってもかまわない。As described above, according to this embodiment, in forming a memory cell capacitor of a semiconductor memory, when the O/N film 6 is formed in an oxygen atmosphere containing trichloroethane, trichloroethane reacts with oxygen and generates chlorine gas and water vapor. ,
The oxidation rate becomes faster, and due to the getter effect of positive ions such as sodium and heavy metals due to chlorine gas, 0/N
The reliability of the film 6 can be improved, and a highly integrated, large-capacity semiconductor memory can be realized. Additionally, trichloroethane has the advantage of being safe to handle. The above manufacturing method is one embodiment of the present invention, and is applicable not only to DRAMs having stacked memory cells but also to trench-type and other semiconductor memories. In addition, the insulating film is O
The present invention is not limited to the /N film, and may be a multilayered film such as a 07N/D film.
また、Ｏ／Ｎ膜６の形成条件（トリクロロエタンの対酸
素流量比や温度、時間等）や第１および第２の導電層３
．７も特に限定されるものではない０
発明の効果
以上のように、本発明の半導体メモリーの製造方法によ
ればトリクロロエタンを含む酸素雰囲気中で信頼性の高
いＯ／Ｎ膜を形成し、このＯ／Ｎ膜を使用してメモリー
セルキャパシタを形成することにより、高集積化された
大容量の半導体メモリーを提供できる。In addition, the conditions for forming the O/N film 6 (trichloroethane to oxygen flow rate ratio, temperature, time, etc.) and the conditions for forming the first and second conductive layers 3
．． 7 is not particularly limited.0 Effects of the Invention As described above, according to the semiconductor memory manufacturing method of the present invention, a highly reliable O/N film is formed in an oxygen atmosphere containing trichloroethane, and this O/N film is formed in an oxygen atmosphere containing trichloroethane. By forming a memory cell capacitor using the /N film, a highly integrated, large-capacity semiconductor memory can be provided.
第１図は本発明の一実施例における半導体メモリーの製
造方法を示す工程図である。
１・・・・・・シリコン基板、２・・・・・・素子分離
絶縁膜、３・・・・・・第１の導電層、４・・・・・・
シリコン窒化膜、５・・・・・・シリコン酸化膜、８・
・・・・・Ｏ／Ｎ膜、７・・・・・・第２の導電層。
代理人の氏名 弁理士 粟 野 重 孝 ＃１か１名ｔ
−−−ｏノへム４（FIG. 1 is a process diagram showing a method for manufacturing a semiconductor memory according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Silicon substrate, 2...Element isolation insulating film, 3...First conductive layer, 4...
Silicon nitride film, 5...Silicon oxide film, 8.
. . . O/N film, 7 . . . second conductive layer. Name of agent: Patent attorney Shigetaka Awano #1 or 1 person
---o no hem 4 (
Claims (1)
形成する工程と、前記第１の導電層上にシリコン窒化膜
を形成する工程と、前記シリコン窒化膜の表面層をトリ
クロロ系ガスを含む酸素ガス雰囲気で酸化する工程と、
同工程で形成した酸化膜上に第２の導電層を形成する工
程を有することを特徴とする半導体メモリーの製造方法
。a step of forming a first conductive layer in a memory cell formation portion on a silicon substrate; a step of forming a silicon nitride film on the first conductive layer; and a step of forming a surface layer of the silicon nitride film containing a trichloride gas. A step of oxidizing in an oxygen gas atmosphere,
A method for manufacturing a semiconductor memory, comprising the step of forming a second conductive layer on the oxide film formed in the same step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63260833A JPH02106959A (en) | 1988-10-17 | 1988-10-17 | Manufacture of semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63260833A JPH02106959A (en) | 1988-10-17 | 1988-10-17 | Manufacture of semiconductor memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02106959A true JPH02106959A (en) | 1990-04-19 |
Family
ID=17353391
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63260833A Pending JPH02106959A (en) | 1988-10-17 | 1988-10-17 | Manufacture of semiconductor memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02106959A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5250456A (en) * | 1991-09-13 | 1993-10-05 | Sgs-Thomson Microelectronics, Inc. | Method of forming an integrated circuit capacitor dielectric and a capacitor formed thereby |
| JP2005045012A (en) * | 2003-07-22 | 2005-02-17 | Matsushita Electric Ind Co Ltd | Manufacturing method of semiconductor device |
-
1988
- 1988-10-17 JP JP63260833A patent/JPH02106959A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5250456A (en) * | 1991-09-13 | 1993-10-05 | Sgs-Thomson Microelectronics, Inc. | Method of forming an integrated circuit capacitor dielectric and a capacitor formed thereby |
| JP2005045012A (en) * | 2003-07-22 | 2005-02-17 | Matsushita Electric Ind Co Ltd | Manufacturing method of semiconductor device |
| JP4545401B2 (en) * | 2003-07-22 | 2010-09-15 | パナソニック株式会社 | Manufacturing method of semiconductor device |
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