JPH02246260A - Manufacture of semiconductor memory device - Google Patents

Abstract

PURPOSE:To make the quality of a dielectric film formed on the surface of an electrode excellent by constituting a spacer required for forming a tree- branch shaped multilayered storage electrode comprising polycrystalline silicon with carbon films, oxidizing the space, vaporizing the spacer in a gaseous state, and removing the gas. CONSTITUTION:A resist process for ordinary photolithography and an RIE method wherein CCl4+O2 (with respect to polycrystalline silicon) and O2 (with respect to C) are used as etching gas are applied. Thus, a polycrystalline silicon film 25, a C film 24, a polycrystalline silicon film 23 and a C film 22 are patterned, and a storage electrode pattern is formed. Then, heat treatment is performed, and the C films 24 and 22 are removed. Thus, the tree-branch shaped multilayered storage electrode is completed. The surface of the polycrystalline silicon films 23, 25 and the like become the very clean states, Thereafter, the quality of a dielectric film 26 which is formed on the surface of the tree-branch type multilayered storage electrode becomes excellent.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] Regarding an improvement in a method for manufacturing a semiconductor memory device having a dendritic multilayer stacked capacitor as a charge storage capacitor in a memory cell, a dendritic portion of a dendritic multilayer storage electrode is configured. The surface of the polycrystalline silicon film can be kept clean when the inclusion film is removed by appropriately selecting the material and removal means for the inclusion film to maintain the interval between the polycrystalline silicon films. The first conductive film and the carbon film are alternately laminated on the substrate, and then the first conductive film and the carbon film are laminated on the substrate. forming an opening reaching from the surface of the film to the surface of the substrate, and then forming a second conductive film that electrically connects and mechanically supports the first conductive film over the entire surface including the inside of the opening. a step of patterning each of the second conductive film, the first conductive film, and the carbon film into a storage electrode shape; and a step of oxidizing the carbon film to make it gaseous and removing it. and,
Next, a step of forming a dielectric film covering all of the exposed surfaces of the second conductive film and the first conductive film, and then filling the space created by removing the carbon film and eliminating the accumulation. The method includes a step of forming a second conductive film patterned into an electrode shape and a third conductive film covering the first conductive film and serving as a counter electrode.

[Industrial application field]

The present invention relates to an improved method of manufacturing a semiconductor memory device having a dendritic multilayer stacked capacitor as a charge storage capacitor in a memory cell.

Currently, dynamic random access memory (
dynamic random accesses
Memory (DRAM) is becoming more highly integrated, and, for example, 16 Mbit devices are about to be put into practical use.

In order to achieve this high degree of integration, memory cells must, of course, be miniaturized.

Normally, a DRAM memory cell consists of a charge storage capacitor part that stores information charges, a transfer gate part made of a transistor that controls the inflow and outflow of charge, and a connection part with wiring. Of these, the charge storage capacitor part is Since it is necessary to store a large amount of charge, the larger the occupied area is, the better; however, in order to achieve the above-mentioned miniaturization, the area must also be reduced. However, it is necessary to ensure a capacity sufficient to store the charges necessary for the DRAM to operate normally.

[Conventional technology]

FIGS. 13 to 16 are cross-sectional side views of essential parts for explaining a conventional DRAM.

In the figure, 1 is a p-type silicon semiconductor substrate, 2 is 5i0
2 is a field insulating film, 41 is a gate electrode made of polycrystalline silicon which is a word line, 5 is an n++ source region which is a bit line contact region, 6 is an n+ type drain region 29 is made of 5i02 in a charge storage capacitor. A dielectric film, 30 is a counter electrode made of polycrystalline silicon in a charge storage capacitor, 31 is an insulating film between the eyebrows, 32
3 indicates a bit line made of Aβ, and 33 indicates a storage electrode made of polycrystalline silicon.

The DRAM shown in Figure 13 is called the Brehner type, and its charge storage capacity depends entirely on the area it occupies in a plane view, so in order to increase the capacity, it is necessary to increase the area it occupies. It is necessary to do so.

The DRAM shown in Figure 14 is called a trench type, and its charge storage capacity can be increased by the size of the trench, but the process control when forming the trench is difficult. It's not easy.

The DRAM shown in Figure 15 is called a stack type, and its charge storage capacity can be increased by the amount of stacking, and it is easier to manufacture than the trench type. There are advantages to this. However, there is a limit to its charge storage capacity.

The DRAM shown in FIG. 16 is of the trenched stack type, and although its charge storage capacity has both the advantages of the trench type and the stack type, it also has drawbacks.

As can be seen from the foregoing, the DRAMs shown in FIGS. 13 to 16 all have drawbacks, and a semiconductor memory device was developed to overcome these drawbacks.

FIG. 27 shows a cutaway side view of essential parts of the improved DRAM, and the same symbols as those used in FIGS. 13 to 16 indicate the same parts or have the same meanings.

In the figure, 48 is a gate electrode made of polycrystalline silicon which is a word line, 7 is an insulating film between eyebrows made of 5i02, 1
2 is a bit line consisting of AJ or W Si 2, 13
is a glabellar insulating film made of S i 3 N 4, 15.17
．． 19 is a polycrystalline silicon film which is a storage electrode of a dendritic multilayer stacked capacitor, and 20 is the same < Si O2
and 21 indicate a counter electrode (cell plate) also made of polycrystalline silicon.

As can be seen from the figure, this DRAM has the advantage of having a so-called dendritic multilayer stacked capacitor, which can dramatically increase the amount of charge stored, and also requires less difficulty in the manufacturing process. There is.

17 to 26 are cross-sectional side views of essential parts of the DRAM at key points in the process for explaining the case of manufacturing the improved DRAM described with reference to FIG. 27,
The same symbols as those used in FIGS. 13 to 16 and FIG. 27 indicate the same parts or have the same meanings.

See FIG. 17 α-1 Selective thermal oxidation using an oxidation-resistant mask such as Si3N film (for example, 1ocal).

xidation of 5ilicon:LOC
By applying the O3) method, a field insulating film 2 made of 5io2 and having a thickness of, for example, about 3000 (people) is formed on a p-type silicon semiconductor substrate 1.

αC-2 The oxidation-resistant mask is removed to expose the active region in the p-type silicon semiconductor substrate 1.

Q7)-3 Similarly, by applying the thermal oxidation method, a gate insulating film 3 made of 5t02 and having a thickness of, for example, about 150 [people] is formed.

Q7)-4 Chemical vapor deposition (chemica I vap).

A polycrystalline silicon film having a thickness of, for example, about 2000 cm is formed by applying a CVD method.

aη-5 Thermal diffusion with source gas as poczi
By applying the l diffusion method,
A polycrystalline silicon film is doped with P.

αC-6 Resist process in normal photolithography technology and reactive ion etching using CCl4 +0□ as etching gas.
By applying an on etching (RIE) method, the polycrystalline silicon film is patterned to form gate electrodes 4+, 4z, etc., which are word lines.

By applying the α Kuuf ion implantation method, As ions are implanted using the gate electrodes 4I and 4f as masks, and heat treatment for activation is performed to form the n++ source region 5, which is the bit line contact region, and the storage electrode. An n+ type drain region 6, which is a contact region, is formed. In this case, the dose of As ions is, for example, 1×l Q”
(cll-”) level and good quality.

Refer to Figure 18 8l-1 By applying the CVD method, a glabellar insulating film 7 made of SiO2 and having a thickness of, for example, about 1000 (people) is formed.The glabellar insulating film 7 is made of Si3N4. Also good.

l-2 By applying a resist process in a normal photolithography technique and an RIE method using an etching gas of CHFff +Q, the glabella insulating film 7 is selectively etched to form the bit line contact window 7A. form.

Referring to FIG. 19, by applying the CVD method, a polycrystalline silicon film having a thickness of, for example, about 500 [layers] is formed.

αl-2 In order to make the polycrystalline silicon film conductive, an ion implantation method is applied to make the polycrystalline silicon film conductive.
In the town, As ions were implanted at an acceleration energy of 50 [KeV].

(To)-3 By applying the CVD method, the thickness can be reduced to, for example, 1000 mm.
A tungsten (W) film of about (1 person) size is formed.

l-4 CCm for resist process and etching gas in normal photolithography technology! By applying the RIE method using 4+oz and SFb, the polycrystalline silicon film and W film are patterned to form the bit line 12.

αt4-5 Heat treatment is performed to cause the polycrystalline silicon in the bit line 12 to react with W to form tungsten silicide (WSi).
z).

Refer to FIG. 20. By applying the CVD method, an etching protective film 13 made of Si 3 N 4 and having a thickness of, for example, about 1"000 is formed.

Referring to FIG. 21, a 5to2 film 14 and a polycrystalline silicon film 15 are formed by applying the CVD method. In this case, the thickness of both may be about 1000 (people).

In order to make the polycrystalline silicon film 15 conductive, an ion implantation method is applied to increase the dose to 4×1015.
(cm-'')% acceleration energy is 50 [KeV], and As ions are implanted.

By applying the CVD method, a SiO2 film 16 and a polycrystalline silicon film 17 are formed. In this case as well,
The thickness of both may be about 1000 mm.

In order to make the polycrystalline silicon film 17 conductive, an ion implantation method is applied to increase the dose to 4×10I5 (
As ions are implanted at an acceleration energy of 50 [KeV].

A 5i02 film 18 is formed by applying the CVD method. The thickness of the 5i02 film 18 is approximately 1000 (people)
degree.

Refer to Figure 22.Resist in normal photolithography technology.
By applying the process and RIE method, 5i02
Selective etching of the film 18 etc. is performed to remove n+ from the surface.
A storage electrode contact window 7B reaching the surface of the type drain region 6 is formed.

In this case, the etching gas is CHF3 +Q for 5io2.

CCβ4+0 for polycrystalline silicon! CHF s + Og for Si3N4 It is better to use each.

By applying the CVD method as shown in FIG. 23, polycrystalline silicon film 19
form. In this case as well, the thickness of the polycrystalline silicon film may be about 1000 (people).

In order to make the polycrystalline silicon film 19 conductive, an ion implantation method is applied to increase the dose to 4×1016.
(elm-''), As ions are implanted at an acceleration energy of 50 (KeV).

Refer to Fig. 24. CC11a +Qt resist process and etching gas in normal photolithography technology.
(for polycrystalline silicon) or CHF5 +Ox-(S
The polycrystalline silicon film 19.5tO2 film 18, polycrystalline silicon film 17, SiO2 film 16, and polycrystalline silicon film 15 were buttered by applying the RIE method (for i02). Form a storage electrode pattern.

By applying the immersion method using hydronic acid, for example, HF: Hz O-1: 10 as an etchant, see Figure 25, 5 tO
2 membranes 18.16.14 are removed.

As is clear from the figure, after this step, a dendritic multilayer storage electrode made of polycrystalline silicon is completed.

By applying the thermal oxidation method as shown in FIG. 26, the polycrystalline silicon film 19 is
．． 17. A thickness of 5io2 on each surface of 15 e.g. 1
A dielectric film 20 of approximately 0.00 (person) is formed.

In this step, instead of the above-mentioned method, a CVD method may be applied to form a dielectric film made of Si3N4 with a thickness of, for example, about 100 [people].

By applying the CVD method (see Fig. 27), a counter electrode (cell
plate) 21 is formed.

The counter electrode 21 is doped with P by applying a thermal diffusion method using P OC1s as a source gas.

CCj etching gas! ! 4 RIE with +O□
The counter electrode 21 is patterned by applying the method.

Although not shown, a pansivation film, bonding pads, backing wiring for lowering the resistance of the word line, wiring, etc. are then formed to complete the process.

Since the semiconductor memory device manufactured in this way has a large-capacity charge storage capacitor made of a dendritic multilayer stacked capacitor, a sufficiently large information signal can be obtained even when miniaturized. The S/N ratio is good, and the resistance to radiation such as α rays is also high. In addition, since a dendritic multilayer stacked capacitor is used, the step difference becomes larger, but since the bit line is formed at the early stage of the process, it is not affected by this, and has many excellent qualities. have.

[Problem to be solved by the invention]

In the manufacturing process of the semiconductor memory device described with reference to FIGS. 17 to 27, as described in step (25)-1 with reference to FIG. 25, in order to form a dendritic multilayer storage electrode, Hydrofluoric acid, e.g. HF: Hz O-
5t by applying the immersion method using 1:10 as an etchant.
The o2 films 18, 16 and 14 are being removed.

When this process is carried out, chemicals, reaction products, dust, etc. remain even after washing with water for quite a long time, and as explained in step (26)-1 with reference to FIG. When the film 20 is formed, there is a problem that a good quality film cannot be obtained. If the dielectric film 20 deteriorates, the leakage current in the dendritic multilayer stacked capacitor will increase, which will interfere with the normal operation of the semiconductor memory device.

The present invention enables the inclusion film to be removed by appropriately selecting the material and removal means for the inclusion film to maintain the spacing between the polycrystalline silicon films constituting the dendritic portion of the dendritic multilayer storage electrode. When removed, the surface of the polycrystalline silicon film is kept clean so that a high quality dielectric film can be formed thereon.

[Means to solve the problem]

In the method for manufacturing a semiconductor memory device according to the present invention, a first conductive film (for example, polycrystalline silicon film 23, etc.) and a carbon film (
for example, carbon films 22, 24, etc.), then forming an opening (for example, storage electrode contact window 7B) reaching from the surface of the laminated film to the substrate surface; forming a second conductive film (for example, polycrystalline silicon film 25) that electrically connects and mechanically supports the first conductive film on the entire surface including the inside of the opening; a step of patterning each of the conductive film, the first conductive film, and the carbon film into a storage electrode shape; then, a step of oxidizing the carbon film to make it into a gaseous state and removing it; A step of forming a dielectric film (for example, dielectric film 26) covering the entire exposed surface of the first conductive film, and then filling the space created by removing the carbon film and forming the storage electrode shape. A third conductive film that covers the second conductive film and the first conductive film and becomes the counter electrode (for example, the counter electrode 2
7).

[Effect]

By adopting the above method, the spacers used in forming the dendritic multilayer storage electrode made of polycrystalline silicon are completely removed, and no chemicals, reaction products, dust, etc. remain. Thereafter, the dielectric film formed on the surface of the dendritic multilayer storage electrode becomes of good quality, and the performance of the dendritic multilayer stacked capacitor, which is a charge storage capacitor, is improved.

〔Example〕

1 to 8 are cutaway side views of essential parts of a DRAM at key points in the process for explaining one embodiment of the present invention.
The same symbols as those used in FIGS. 16 to 16 and 17 to 27 indicate the same parts or have the same meanings. In this embodiment, the glabella insulating film 13'
The steps up to the formation of the etching protection film 13 (in the prior art) are the same as those of the prior art described with reference to FIGS. 17 to 27, and therefore will be explained from the stage of forming the glabella insulating film 13.

See Figure 1 By applying the CVD method, Si3N.

A glabellar insulating film 13' having a thickness of, for example, about 1000 (people) is formed.

Refer to FIG. 2. For example, by applying a CVD method that utilizes the thermal decomposition of methane, that is, the reaction CH4→C+H ↑, a carbon (C) film 22 is formed. In this case, the thickness is, for example, approximately 1000 (persons).

By applying the CVD method, the polycrystalline silicon film 23
form. In this case, the thickness is approximately 1000 (people)
It's fine to a certain degree.

In order to make the polycrystalline silicon film 23 conductive, an ion implantation method is applied to increase the dose to 4X1015 (value -
:], As ions are implanted at an acceleration energy of 50 (KeV).

A C film 24 is formed by applying the CVD method.

In this case, the thickness is, for example, about 1000 people.

Refer to FIG. 3 By applying the resist process and RIE method in ordinary photolithography technology, selective etching of the C film 24, etc. is performed to remove the accumulation reaching the surface of the n+ type drain region 6 from the surface. An electrode contact window 7B is formed.

In this case, the etching gas is 0 for C! CCIla + 0xSisN for polycrystalline silicon,
It is better to use CI(F3+O!) for each.

By applying the CVD method (see FIG. 4), polycrystalline silicon film 25
form. In this case as well, the thickness of the polycrystalline silicon film may be about 1000 (people).

In order to make the polycrystalline silicon film 19 conductive, an ion implantation method is applied to increase the dose to 4×1016 (particles).
9. Implant A8 ions with acceleration energy of 50 (KeV).

Refer to FIG. 5. CC11a +OR(
) and 0! By applying the RIE method (for C), the polycrystalline silicon film 25
, the C film 24, the polycrystalline silicon film 23, and the C film 22 are patterned to form a storage electrode pattern.

The C films 24 and 22 are removed by heat treatment in a snow-free atmosphere at a temperature of about 300 to 900 ('C), for example, as shown in FIG.

Here, the C films 24 and 22 are removed from C+0. -〇〇t ↑ It depends on the reaction.

As is clear from the figure, after this step, a dendritic multilayer storage electrode made of polycrystalline silicon is completed. Note that as a technique to be applied to this step, an isotropic 0° plasma etching method may be applied instead of heat treatment in an O8 atmosphere; in any case, in this case, there will be no residue. , the surfaces of the polycrystalline silicon films 23, 25, etc. become extremely clean.

Referring to FIG. 7, by applying the CVD method, a dielectric film 26 made of Si3N4 having a thickness of, for example, about 100 [layers] is formed.

This structure is achieved by applying a thermal oxidation method instead of the above-mentioned means, so that each surface of the polycrystalline silicon films 23 and 25 has a
A dielectric film made of tO2 and having a thickness of, for example, about 100 [people] may be formed.

By applying the CVD method (see Fig. 8), a counter electrode (cell
plate) 27 is formed.

The counter electrode 21 is doped with P by applying a thermal diffusion method using P OCl s as a source gas.

RIE using etching gas as CCIta + Ot
The counter electrode 21 is patterned by applying the method.

Although not shown in the drawings, a puffy bassin film, bonding pads, backing wiring for lowering the resistance of the word line, wiring, etc. are then formed to complete the process.

The quality of the dielectric film 26 in the semiconductor memory device thus manufactured was extremely good.

FIGS. 9 to 12 are cross-sectional side views of essential parts for explaining a configuration example of a dendritic multilayer stacked capacitor, and the same symbols as those used in FIGS. 1 to 8 refer to the same parts. or have the same meaning.

The dendritic multilayer stacked capacitor shown in FIG. 9 has a structure in which dendritic portions are bundled at the center.

In the dendritic multilayer stacked capacitor shown in FIG. 10, the dendritic portions are bundled at the ends.

In the dendritic multilayer stacked capacitor shown in FIG. 11, the dendritic portions are bundled in the center, and the storage electrode is at the bottom layer of the dendritic portions.

In the dendritic multilayer stacked capacitor shown in FIG. 12, the dendritic portions are bundled at the center, and the opposing electrode is the lowest layer in the dendritic portion.

〔Effect of the invention〕

In the method for manufacturing a semiconductor memory device according to the present invention, a spacer required when forming a tree-like multilayer storage electrode made of polycrystalline silicon is formed of a carbon film, and when it is removed, an oxidized This turns it into a gas and diffuses it.

By adopting the above structure, the spacer is completely removed, and there is less remaining of chemicals, reaction products, dust, etc. Therefore, the dielectric film formed on the surface of the dendritic multilayer storage electrode is This improves the performance of dendritic multilayer stacked capacitors, which are charge storage capacitors.

[Brief explanation of drawings]

1 to 8 are cross-sectional side views of essential parts of a semiconductor memory device at key points in the process for explaining one embodiment of the present invention, and FIGS. 9 to 12 are configurations of a dendritic multilayer stacked capacitor. Main part cutaway side views for explaining examples, Figures 13 to 1
Figure 6 is a cutaway side view of the main parts to explain the conventional DRAM.
FIGS. 17 to 27 are cross-sectional side views of essential parts of a semiconductor memory device at key points in the process for explaining a conventional example. In the figure, 1 is a p-type silicon semiconductor substrate, 2 is an Si
4. field insulating film made of O2; and 4. 5 is an n+ type source region which is a bit line contact region, 6 is an n+ type drain region, 7 is a glabella insulating film made of 5102, and 13 is an etching protection film made of Si3N4. , 13'
22 and 24 are carbon films, 23 and 25 are polycrystalline silicon films, 2
Reference numeral 6 indicates a dielectric film, and reference numeral 27 indicates a counter electrode made of polycrystalline silicon. Patent Applicant Fujitsu Ltd. Representative Patent Attorney Shoji Sutani Representative Patent Attorney Hiroshi Watanabe - Cutaway side view of essential parts of semiconductor memory device Figure 1 Figure 3 Cutaway side view of essential parts of semiconductor memory device Figure 2 6. A cutaway side view of the main parts of a semiconductor memory device. A cutaway side view of the main parts of a semiconductor memory device. Cutaway side view Figure 10 Main part cutaway side view 1st to explain the conventional 1m) RAM
Figure 3: A cut-away side view of essential parts to explain a conventional DRAM. Figure 14: A cut-away side view of essential parts to explain a conventional DRAM. Figure 15: A cut-away side view of essential parts to explain a conventional DRAM. (Fig. 19 is a cut-away side view of the main part of the semiconductor memory device; Fig. 19 is a cut-away side view of the main part of the semiconductor memory device at key points in the process; Fig. 2 is a cut-away side view of the main part of the semiconductor memory device at key points in the process)
Figure 0: Cutaway side view of the main part of the semiconductor memory device at the key point in the process Figure 18: Cutaway side view of the main part of the semiconductor memory device at the key point in the process Figure 18: Cutaway of the main part of the semiconductor memory device at the key point in the process Side view Fig. 21 Fig. 22 Cutaway side view of the main part of the semiconductor memory device at key points in the process Second
Figure 4: Second cutaway side view of the main parts of the semiconductor memory device at key points in the process
Figure 3: Second cutaway side view of the main parts of the semiconductor memory device at key points in the process.
Figure 5: Key points in the process: Cutaway side view of main parts of semiconductor memory device Figure 26 Figure 27

Claims (1)

[Claims] A step of alternately layering a first conductive film and a carbon film on a substrate, a step of forming an opening that reaches the surface of the substrate from the surface of the layered film, and then , forming a second conductive film that electrically connects and mechanically supports the first conductive film on the entire surface including the inside of the opening; a step of patterning each of the conductive film and the carbon film in the shape of a storage electrode; then a step of oxidizing the carbon film to make it into a gaseous state and removing it; a step of forming a dielectric film covering all of the exposed surface of the carbon film; and a second conductive film patterned in the shape of the storage electrode and a first conductive film filling the space created by removing the carbon film. A method for manufacturing a semiconductor memory device, comprising the step of forming a third conductive film covering the film and serving as a counter electrode.