JPH0456265A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable the capacitor of a DRAM to be enlarged in capacitance by a method wherein irregularities are provided to the surface of the charge storage part of a stacked type memory cell in a self-aligned manner. CONSTITUTION:An interlaminar insulating film provided with an opening, a polysilicon film 3, and a first oxide film 4 are formed on a silicon substrate 1, the first oxide film 4 is removed through etching excluding a required region, a first silicon nitride film 6 is formed, and the first silicon nitride film 6 is left unremoved only on the side wall of the first oxide film 4 through etching. Then, the same process is repeated to form a second oxide film 7 and a second silicon nitride film 8. In succession, the polysilicon film 3 is etched using these films as a mask, the first oxide film 4 and the second oxide film 7 are selectively removed, the polysilicon film 3 is etched using the first silicon nitride film 6 and the second silicon nitride film 7 left unremoved as a mask, the outside polysilicon film 3 is completely removed from the second silicon nitride film 8, and the first silicon nitride film 6 and the second silicon nitride film 8 are removed by etching solution.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device for a charge storage section of a stacked cell of a dynamic random access memory (hereinafter referred to as DRAM).

BACKGROUND OF THE INVENTION Various memory cell structures have been proposed to realize large capacity DRAMs. One such example is a stacked memory cell in which a charge storage section is read out and stacked on top of a transistor.

In stacked memory cells, various efforts have been made to increase the surface area of the charge storage portion.

Figure 3 is announced for 64 megabits (double).

Wakamiya et al., V.L.N.I. Symposium Technical Digest (W, Wakamiya
et al, VLSI Symp, Tech, Dig,
), ])69 (1989)) shows a method of manufacturing a charge storage section.

To briefly explain this conventional manufacturing method, first, Figure 3 +
As shown at a+, a first polysilicon film 33 is formed on an interlayer insulating film 32 formed on a silicon substrate 31. This first polysilicon film 33 is connected to the silicon substrate 31 through an opening formed in the interlayer insulating film 32.

Next, a CVD film 34 is formed on the first polysilicon film 33, and as shown in FIG. do.

Next, the photoresist film 37 is transferred to the second polysilicon film 3.
CVD film 3 is coated on top of CVD film 3 using a well-known etch-back method.
The polysilicon film 36 on the film top 4 and the top 2 is removed. Figure 3 (
C1 indicates this state.

Finally, the photoresist film 37 remaining in the opening 35 and the CVD film 34 are removed to complete the charge storage portion of the stacked memory cell shown in FIG. 3(dl).

Problems to be Solved by the Invention However, in the conventional manufacturing method shown in FIG. 3, as shown in FIG.
The alignment margin (j!m
)Is required. For this reason, conventional manufacturing methods have had the problem of not being able to cope with further miniaturization of memory cells.

Means for Solving the Problems The present invention has been made to solve the above problems, and includes a step of forming a first base protective film made of a silicon oxide film in a desired region on a conductor made of a polysilicon film. and,
A step of forming a second base protective film made of a silicon nitride film in contact with the side wall portion of the first base protective film and the surface of the conductor, and repeating the same process at least once to form a second base protective film on the surface of the conductor. a step of alternately forming a first base protective film and a second base protective film; a step of etching the conductor using the first base protective film and the second base protective film as masks; and a step of etching the conductor using the first base protective film and the second base protective film as masks. A step of removing either the film or the second base protective film to expose a part of the surface of the conductor, and then removing the exposed conductor using the remaining first or second base protective film as a mask. It consists of a process of etching a portion.

Effect: With this configuration, unevenness can be formed on the surface of the charge storage part of the stacked memory cell by the self-alignment line, so that D
It becomes possible to expand the capacity of the RAM capacitor.

Embodiment Below, an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention using a method for forming a lower electrode of a charge storage portion of a stacked memory cell is shown in FIGS. This will be explained with figures.

First, as shown in FIG. 1(a), a film 9 is formed on an interlayer insulating film 2 having an opening formed on a silicon substrate 1.
A polysilicon film 3 having a thickness of 2 μm is formed by a well-known low pressure CVD method, and then a first oxide film (SiO=film) 4 having a film thickness of 400 nm is formed by a well-known CVD method. Furthermore, a photoresist film 5 having a width of about 0.6 μm is formed in a desired region on the first oxide film 4 by a normal photolithography method. Next, using the photoresist film 5 as a mask, the first oxide film 4 is removed by a well-known reactive ion etching method.

Next, as shown in FIG. is formed by a well-known low pressure CVD method.

Next, the first silicon nitride film 6 is subjected to reactive ion etching to leave the first silicon nitride film 6 only on the side wall portions of the first oxide film 4, as shown in FIG. 1(C). Next, the same process is repeated to form a second oxide film (SiO2 film) 7 with a thickness of 250 nm, and a second oxide film (SiO2 film) with a thickness of 250 nm.
A silicon nitride film 8 is formed in the shape shown in FIG. 1(C). At this time, the width of each film formed on the side wall of the first oxide film 4 becomes approximately equal to the film thickness immediately after formation, and as shown in FIG. The total width of the first silicon nitride film 6, the second oxide film 7, and the second silicon nitride film 8 is approximately 0.6+2x (0,25+0 , 25 + 0
825)=about 2.1 μm.

Next, as shown in FIG. 1(d), a first oxide film 4, a first silicon nitride film 6. Using both the second oxide film 7 and the second silicon nitride film 8 as a mask, the polysilicon film 3 is
is etched to a depth of approximately 0.6 μm using a reactive ion etching method.

Next, as shown in FIG. 1(e), the first oxide film 4 and the second oxide film 7 are coated with a mixed solution of hydrofluoric acid and ammonium fluoride (NH4
Selectively remove with F:HF=5:1).

Next, using the remaining first silicon nitride film 6 and second silicon nitride film as masks, the polysilicon film 3 is etched to a depth by reactive ion etching as shown in Figure 1). Etching is performed to approximately 0.69 μm. By doing this, initially about 0.6μ
The outer polysilicon film 3 is completely removed from the second silicon nitride film 8 which has been etched by about m. On the other hand, the portion of the polysilicon film 3 that was covered by the oxide film 4 and the second oxide film 7 in solution 1 is etched by about 0.9 μm.
A polysilicon film with a thickness of approximately 1.2-0.9 = 0.3 μm remains at the bottom.

Finally, the structure shown in FIG. 1+g+ is obtained by removing the first silicon nitride film 6 and the second silicon nitride film 8 using a well-known phosphoric acid etching solution. Note that by using the method described above, it is possible to manufacture a structure having a ring, a single row, or other complex shapes.

Next, FIG. 2 shows an embodiment in which an n-channel stacked memory cell is formed by applying the present invention.

To explain the manufacturing method of the memory cell shown in Fig. 2,
A field oxide film 12 is formed on a p-type silicon substrate 11 by a well-known selective oxidation method, and then a gate oxide film 13 constituting a selection transistor is formed. A gate electrode (word line) 14 and an n° diffusion layer 15 are formed. Next, after covering the gate electrode 14 with the first interlayer insulating film 16, the lower electrode 17 of the charge storage section is formed by the manufacturing method explained in FIG.

Next, after forming a capacitor insulating film 18 on the surface of the lower electrode 17, a capacitor plate electrode 19 is formed. next,
A stacked memory cell is formed by forming a second interlayer insulating film 20 and connecting the bit line 21 to one n+ diffusion layer 15 through the contact window opening.

In the present embodiment shown in FIG. 1, the lower electrode of the charge storage section has a double structure, but it is also possible to have a triple or quadruple structure. Further, in this embodiment, as shown in FIG. 1(C),
The base protective film was formed sequentially from the first oxide film 4 toward the outside, but in contrast, the base protective film was first formed on the outer periphery, and then the base protective film was formed sequentially toward the center. Of course, it is also possible to do so.

Effects of the Invention As described above, according to the present invention, it is possible to increase the surface area of the charge storage part in a self-aligned manner, and a large capacitance can be formed in a small area, so that the memory cell of a DRAM can be greatly expanded. It has the effect of being able to be made smaller.

[Brief explanation of the drawing]

Figures 1(a) to (gl are step-by-step sectional views for explaining the manufacturing method of the present invention, Figure 2 is a DRAM to which the present invention is applied)
A cross-sectional view of a stacked memory cell in Figure 3 (al~(
d) is a step-by-step sectional view for explaining a conventional manufacturing method. 1...Silicon substrate 1.3...Polysilicon film (conductor), 4...First oxide film (first base protective film), 6... . . . first silicon nitride film (second underlying protective film), 7 . . . second oxide film, 8 . . . second silicon nitride film. Name of agent Patent attorney Shigetaka Awano and 1 other person N~ Condolences (h Funeral map Figure 3 (b) (C) (d,)

Claims (2)

[Claims] (1) Forming a first base protective film in a desired area on a conductor formed on a silicon substrate, and forming a second base protective film on the side wall portion of the first base protective film and the surface of the conductor. a step of forming a protective film; a step of repeating the same step at least once to alternately form the first base protective film and the second base protective film on the surface of the conductor; etching the conductor using the base protective film and the second base protective film as masks; and removing either the first base protective film or the second base protective film to remove the conductive material. A method for manufacturing a semiconductor device, comprising the steps of exposing a part of the surface of the body, and etching the exposed part of the conductor using the remaining underlying protective film as a mask. (2) The method of manufacturing a semiconductor device according to claim 1, wherein the conductor, the first base protective film, and the second base protective film are a polysilicon film, a silicon oxide film, and a silicon nitride film, respectively.