JPH02106870U - - Google Patents

Info

Publication number
JPH02106870U
JPH02106870U JP1457989U JP1457989U JPH02106870U JP H02106870 U JPH02106870 U JP H02106870U JP 1457989 U JP1457989 U JP 1457989U JP 1457989 U JP1457989 U JP 1457989U JP H02106870 U JPH02106870 U JP H02106870U
Authority
JP
Japan
Prior art keywords
wiring board
printed wiring
pattern
land
drawn
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1457989U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1457989U priority Critical patent/JPH02106870U/ja
Publication of JPH02106870U publication Critical patent/JPH02106870U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第2図はそれぞれ本考案によるプリン
ト配線板のICパターン形状の実施例を示す図、
第3図は従来のプリント配線板のICパターン形
状例を示す図である。 図面中、1はプリント配線板、2はIC、3A
はリード、4Aは捨てランド、5は電源、接地、
共通電位あるいは信号のパターン、6は捨てパタ
ーンである。
FIG. 1 and FIG. 2 are diagrams showing examples of the IC pattern shape of a printed wiring board according to the present invention, respectively;
FIG. 3 is a diagram showing an example of the shape of an IC pattern on a conventional printed wiring board. In the drawing, 1 is a printed wiring board, 2 is an IC, and 3A
is the lead, 4A is the discarded land, 5 is the power supply, ground,
The common potential or signal pattern 6 is a discarded pattern.

Claims (1)

【実用新案登録請求の範囲】 IC用ランドが形成され、前記IC用ランドの
うち電源、接地、共通電位及び信号いずれのパタ
ーンも引き出されていない捨てランドが存在する
プリント配線板において、 捨てランドのみから引き出された捨てパターン
が形成されていることを特徴とするプリント配線
板のICパターン形状。
[Scope of Claim for Utility Model Registration] In a printed wiring board where an IC land is formed and there is a waste land among the IC lands from which no power, ground, common potential, or signal pattern is drawn out, only the waste land. 1. An IC pattern shape of a printed wiring board, characterized in that a discarded pattern drawn from a wafer is formed.
JP1457989U 1989-02-13 1989-02-13 Pending JPH02106870U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1457989U JPH02106870U (en) 1989-02-13 1989-02-13

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1457989U JPH02106870U (en) 1989-02-13 1989-02-13

Publications (1)

Publication Number Publication Date
JPH02106870U true JPH02106870U (en) 1990-08-24

Family

ID=31225906

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1457989U Pending JPH02106870U (en) 1989-02-13 1989-02-13

Country Status (1)

Country Link
JP (1) JPH02106870U (en)

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