JPH0210608U

JPH0210608U -

Info

Publication number: JPH0210608U
Application number: JP8883188U
Authority: JP
Priority date: 1988-07-04
Filing date: 1988-07-04
Publication date: 1990-01-23

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例の構成図で、ａは斜
視図、ｂは鎖線Ｘ−Ｘ部の断面図、ｃは鎖線Ｙ−
Ｙ部の断面図、第２図は従来例の構成図で、ａは
斜視図、ｂは鎖線Ｘ−Ｘ部の断面図、第３図は他
の従来例の構成図で、ａは斜視図、ｂは裏面視の
斜視図である。図において、１，１−１，１−２，１０−１，
１０−２は誘電体基板、２，２−１，２−２，３
１，３２，３３は遅延線パターン、３−１，３−
２，１３−１，１３−２はアース電極、４は入出
力端子、５はアース端子、１５は橋絡線、２ａ，
２ｂ，２１ａ，３１ａ，３１ｂ，３２ａ，３２ｂ
は端末パツド、２１ｂ，２２ｂは上部端末をそれ
ぞれ示す。 FIG. 1 is a block diagram of an embodiment of the present invention, in which a is a perspective view, b is a sectional view taken along chain line X-X, and c is a cross-sectional view taken along chain line Y-X.
A sectional view of the Y part, FIG. 2 is a configuration diagram of a conventional example, a is a perspective view, b is a sectional view taken along the chain line X-X, FIG. 3 is a configuration diagram of another conventional example, and a is a perspective view , b are perspective views as viewed from the back. In the figure, 1, 1-1, 1-2, 10-1,
10-2 is a dielectric substrate, 2, 2-1, 2-2, 3
1, 32, 33 are delay line patterns, 3-1, 3-
2, 13-1, 13-2 are ground electrodes, 4 is an input/output terminal, 5 is a ground terminal, 15 is a bridge wire, 2a,
2b, 21a, 31a, 31b, 32a, 32b
indicates a terminal pad, and 21b and 22b indicate upper terminals, respectively.

Claims

[Claims for Utility Model Registration] Delay line patterns 2-1 and 2-2 of the same shape meandering left and right as desired and having a terminal pad near the lower edge
are formed on the front surface of each substrate, and ground electrodes 3-1, 3-2 are formed on the back surface of the pair of dielectric substrates 1-1, 1-2, which are shifted in the left-right direction and are closely attached back-to-back. and the upper terminal 2 of the delay line patterns 2-1 and 2-2.
1b and 22b, and input/output terminals 4 which are soldered and fixed to the terminal pads near the lower edges of the delay line patterns 2-1 and 2-2, respectively. A delay element characterized in that it is provided with a ground terminal 5 which is soldered and fixed to the left and right portions of the dielectric substrates 1-1 and 1-2.