JPH02105565A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a bipolar element or a MOS element optionally with each semiconductor by laminating alternately an insulating film and semiconductor layers on a semiconductor substrate and then, by introducing and diffusing impurities into the exposed faces of respective semiconductor layers after treating semiconductor layers on each layer. CONSTITUTION:An SiO2 film, a silicon single crystal layer 3, an SiO2 film 4, a silicon single crystal layer 5, and an SiO2 film 6 are laminated one after another on a silicon substrate 1 equipped with a horizontal bipolar transistor for power which is made by forming in advance a P-type base layer 12 in an N-type collector 11 and further forming an emitter layer 13 in the P-type layer. Then, exposed faces which are lacking in respective upper semiconductor layers are formed on the semiconductor layers 3 and 5. Impurities are introduced and diffused from the exposed faces of the above layers 3 and 5 and semiconductor elements are formed on the above layers 3 and 5. The elements having different intrinsic impurity diffusion depths are made by separating them into each chip.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a power semiconductor device in which bipolar elements, 0MO3 elements, blade elements, etc. are integrated on the same chip.

[Conventional technology]

For example, the book ``Physics, Design and Seven Building Sciences''
nd^pplications) J New York, McGraw-Hill, Inc. 19
Published in 1986, or published in the magazine “Electronics (Ele
ctronlcs) J December 29, 1982 issue 5
As described in the May 31, 1984 issue of the same magazine, page 87, and the August 5, 1985 issue, page 40 of the same magazine, conventional integration methods are , is based on forming and separating junctions by selectively diffusing impurities. This is a technology and method that is an extension of the semiconductor process that brought about the rise of IC technology with the establishment of Brainer technology.

[Problem to be solved by the invention]

Since the basis of such conventional integration methods is the selective diffusion method of impurities, when integrating a bipolar element CMO3 element and a blade element on the same chip, the following two problems must be solved. There must be.

How to control the differences in the depth of impurity diffusion caused by the unique characteristics of each element, such as +11 bipolar elements, 0MO3 elements, and i-blade elements, and how to design a series of processes.

(2) When building bipolar elements, CMO5 elements, power elements, etc. on the same chip, how should these elements be separated?

The basic idea behind the prior art solution to the problem in item (1) is to form elements in order starting from those requiring deep junctions. Generally, power elements.

Bonding is performed in the order of the bipolar element and the CMO3 element.

By doing so, the idea is to minimize fluctuations and dispersion in junction depth due to thermal history during the process of sequentially forming junctions for individual elements. However, with this conventional approach, there are many repetitions of the impurity diffusion process and the photo process for selectively diffusing the impurities, which tends to increase the number of steps and make it complicated. Decreased retention.

Even if it was intended to minimize fluctuations and variations in the junction depth of individual elements, there were problems such as the presence of an uncertain element in which nothing could be said until the GK Hiiragi process was completed.

Junction isolation is the mainstream solution to the problem in item (2) in the prior art, but it is difficult to miniaturize due to constraints such as the need for relatively high concentration and deep diffusion to separate the power element part. , there were problems such as easy latch-up.

The object of the present invention is to solve the above problems and eliminate the inherent impurity l
11. It is an object of the present invention to provide a method for manufacturing a semiconductor device, which allows elements having different depths to be separated into one chip and easily fabricated.

(Means for Solving i!Ifl) In order to solve the above problem, the method for manufacturing a semiconductor device of the present invention includes alternately stacking insulating layers and semiconductor layers on a semiconductor substrate having an impurity diffusion layer. , an exposed surface where no upper semiconductor layer exists is formed in each semiconductor layer, and impurities are introduced from the exposed surface of each semiconductor layer.

A semiconductor element is formed in each semiconductor layer by diffusion. [Operation] The diffusion depth of a semiconductor element formed in semiconductor layers laminated via an insulating layer is uniquely determined by the thickness of the semiconductor layer. be done. In addition, since the impurity diffusion layer is formed in the upper layer of each layer where it does not exist, each impurity diffusion can be performed in one step.

〔Example〕

FIG. 1 (al to +d+ shows an embodiment of the present invention, in which a power vertical bipolar transistor is made by forming a P base JH12 in an N collector N11 and an N emitter eyebrow 13 therein in advance). s on the existing silicon substrate 1
lo, membrane 2. Sequentially stack silicon single crystal layer 3, SIO, film 4, silicon single crystal N5 *Sin, film 6 (
Figure a) * sio, silicon single crystal layer 3 on membranes 2, 4.
5 can be obtained, for example, by depositing polycrystalline silicon and then laser annealing it. The number of laminated layers is determined by how many types of devices are to be made simultaneously. In addition, the thickness of the SiJ film and the thickness of the silicon single crystal are determined by the device to be fabricated. Next, 5iots of silicon are deposited on top of the first silicon single crystal layer 3 by a normal photo process until the first layer 3 is exposed.
Layer 4. A partial trenching process is performed on the single crystal 1155° sro nitride N6 (Fig. b), and impurities are selectively diffused into the silicon single crystal N3 from the resulting exposed surface to collector layer 31. A base layer 32 and an emitter layer 33 are formed, and a horizontal N
At the same time as forming a PN bipolar transistor, an acceptor impurity is also diffused into the silicon single crystal layer 5 to form a P well 51.
2.53 is formed, and a gate electrode 7 is provided on the 5iOxa6 using a polycrystalline silicon layer, and a MOSFET is fabricated on the same substrate (Figure d).The bipolar transistor section of the silicon single crystal layer 3 is formed in 6 or more steps. When forming the diffusion layer of the MOSFET part of the silicon single crystal layer 5, it is possible to form it under the same drive conditions by simply selecting the dimensions of the photomask, the thickness of each silicon single crystal layer 3.5, and the dose of impurity implantation. Therefore, the heat treatment process can be reduced to about 1/2 of the conventional process, and a diffusion layer with a desired impurity concentration can be easily formed.

FIG. 2 shows a semiconductor device formed by substantially the same process as in FIG. 1, in which the substrate 1 is a substrate 1 made by epitaxially growing NJI on an N° substray (10) to a total thickness of 525 am. The thickness of the lateral bipolar transistor is determined by the thickness of the silicon single crystal N3, and the thickness of the MOSFET is determined by the thickness of the silicon single crystal layer 5. Their thickness is of the order of 1-.

Also, the width of the source/drain region 53 is equal to the width of the silicon single crystal 1
Determined by the dimensions of the groove digging process in step 5. Although not shown in the figure,
Wiring is connected through contact holes provided in each 5-ins membrane.

FIG. 3 shows another embodiment in which the P base layer 14. Power MO3) transistor base Fi with N” emitter layer 15 formed
A Sing film 2, 4.6 and a silicon single crystal layer 3.
First, a silicon single crystal layer 3 with a high impurity concentration is processed to provide a gate electrode 8 of a power MO3) transistor. Other parts of the single crystal layer 3 can be used for forming other elements by trenching the upper layer. The second silicon single crystal layer 5 is used as a substrate for a MOS or 0MO3) transistor, and the P well 51. So, -s and drain regions 52 and 53 and a gate electrode 7 are formed. As a result, a power section made up of power transistors and a control section made up of MOSFETs are integrated into one chip.

〔Effect of the invention〕

According to the present invention, insulating films and semiconductor layers are alternately stacked on a semiconductor substrate on which a power device can be formed, and the upper semiconductor layer is processed to introduce and diffuse impurities into the exposed surface of each semiconductor layer. , it has become possible to arbitrarily form bipolar elements or MO3 elements for each semiconductor layer. and,
Since the isolation between elements is performed three-dimensionally using an insulating film, there is no need for junction isolation (and the degree of integration has improved. Also, there is no need to repeat the impurity diffusion process and photo process, and the thickness of each element can be reduced. Since the layer thickness is automatically limited, the manufacturing process is extremely simplified.

[Brief explanation of drawings]

FIG. 1 (Ill to +d+ are sectional views sequentially showing the manufacturing steps of an embodiment of the present invention, FIG. 2 is a partial sectional view of a semiconductor device manufactured by the steps shown in FIG. 1, and FIG. 3 is a partial sectional view of a semiconductor device manufactured by the steps shown in FIG. 1. It is a partial sectional view of a semiconductor device manufactured by another example of the present invention. 1: Silicon substrate, 2, 4, 6: Sho, film, 3
．． 5: silicon single crystal layer, 7.8: gate electrode, 11,
31; N collector layer, 12.14, 32: P base layer, 13.15.33 jN emitter layer. 1 no 14-7~. ·Ku·

Claims (1)

[Claims] 1) Alternately stacking insulating layers and semiconductor layers on a semiconductor substrate having an impurity diffusion layer, forming an exposed surface in each semiconductor layer where no upper semiconductor layer is present, and introducing impurities from the exposed surface of each semiconductor layer, A method for manufacturing a semiconductor device, comprising forming a semiconductor element in each semiconductor layer by diffusion.