JPH02102535A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH02102535A JPH02102535A JP25625588A JP25625588A JPH02102535A JP H02102535 A JPH02102535 A JP H02102535A JP 25625588 A JP25625588 A JP 25625588A JP 25625588 A JP25625588 A JP 25625588A JP H02102535 A JPH02102535 A JP H02102535A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- wirings
- constituted
- integrated circuit
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 239000004020 conductor Substances 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 2
- 239000010408 film Substances 0.000 abstract 5
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- 239000010409 thin film Substances 0.000 abstract 1
- 239000011229 interlayer Substances 0.000 description 5
- 230000001681 protective effect Effects 0.000 description 5
- 238000005530 etching Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000011093 chipboard Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路装置に関し、特に微細配線を備
えた半導体集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device having fine wiring.
〔従来の技術］
従来の半導体集積回路装置は、第３図（ａ）及び（ｂ）
に夫々平面図、及びＣ−Ｃ線断面図を示すように、半導
体チップの基板１１上に均一厚さの導体膜を形成し、こ
れを所要パターンにエツチングしてトランジスタ、抵抗
等の各種素子間を接続する配線１２を形成している。な
お、１３は保護絶縁膜である。[Prior Art] A conventional semiconductor integrated circuit device is shown in FIGS. 3(a) and (b).
As shown in the plan view and the cross-sectional view taken along the line C-C, a conductive film of uniform thickness is formed on the substrate 11 of the semiconductor chip, and this is etched into a desired pattern to connect various elements such as transistors and resistors. A wiring 12 is formed to connect the two. Note that 13 is a protective insulating film.
上述した従来の半導体集積回路装置では、全ての配線を
均一厚さの導体膜で形成しているため、導体膜の厚さは
大電流を流す配線を基準に設定している。このため、導
体膜の厚さを薄くすることが困難であり、露光技術やエ
ツチング技術の制約から微細幅の配線を形成することが
難しく、この結果、微小電流しか流さない配線において
も配線幅が大きくなり、配線の微細化を進める上での障
害になっている。In the conventional semiconductor integrated circuit device described above, all the wiring is formed of a conductive film having a uniform thickness, so the thickness of the conductive film is set based on the wiring through which a large current flows. For this reason, it is difficult to reduce the thickness of the conductor film, and it is difficult to form interconnections with minute widths due to limitations in exposure and etching techniques. This has become an obstacle to the progress of miniaturization of interconnects.
本発明は微小電流を流す配線の微細化を可能とした半導
体集積回路装置を提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device that enables miniaturization of wiring through which minute currents flow.
本発明の半導体集積回路装置は、基板上に薄い導体膜で
形成した第１配線と、この第１配線上に選択的に重ねて
被着した導体膜で形成した第２配線とを備え、一部の配
線を第１配線のみで構成し、他の配線を第１配線と第２
配線の積層構造で構成している。A semiconductor integrated circuit device of the present invention includes a first wiring formed of a thin conductive film on a substrate, and a second wiring formed of a conductive film selectively overlaid and deposited on the first wiring. The wiring in the section consists of only the first wiring, and the other wiring consists of the first wiring and the second wiring.
It consists of a layered structure of wiring.
上述した構成では、第１配線を微細に形成でき、微小電
流用配線の微細化を実現するとともに、第１配線と第２
配線の積層により大電流用配線を充分厚く構成できる。In the above-mentioned configuration, the first wiring can be formed finely, the fine current wiring can be realized, and the first wiring and the second wiring can be formed finely.
By stacking the wiring, the wiring for large current can be configured to be sufficiently thick.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）及び（ｂ）は本発明の第１実施例の平面図
、及びそのＡ−Ａ線に沿う断面図である。FIGS. 1(a) and 1(b) are a plan view of a first embodiment of the present invention and a cross-sectional view thereof taken along line A-A.
図において、半導体チップ基Ｆｉｌ上には０．５μｍ程
度の薄い導体膜を形成し、これを所要パターンにエツチ
ングして第１配線２を形成している。また、この第１配
線２上には０．５μｍの導体膜を重ねて形成し、かつこ
れをエツチングして前記第１配線２の選択された領域に
のみ第２配線３を形成している。この結果、第１配線２
のみの薄い膜厚（０，５μｍ）の配線と、第１配線２と
第２配線３を積層した厚い膜厚（１，０μｍ）の配線と
で構成される。なお、４は保護絶縁膜である。In the figure, a thin conductor film of about 0.5 μm is formed on the semiconductor chip base Fil, and the first wiring 2 is formed by etching this into a desired pattern. Further, a conductor film of 0.5 μm is formed overlyingly on the first wiring 2, and this is etched to form the second wiring 3 only in a selected region of the first wiring 2. As a result, the first wiring 2
The first wiring 2 and the second wiring 3 are stacked to form a thick wiring (1.0 .mu.m). Note that 4 is a protective insulating film.
したがって、微小電流を流す配線は第１配線２のみで構
成し、比較的大電流を流す電源等の配線は第１配線２と
第２配線３を重ねた構成とすればよい。これにより、微
小電流用配線の形成に際しては、薄い導体膜を用いて露
光、エツチングを行うため、微細な配線を形成できる。Therefore, the wiring through which a small current flows may be composed of only the first wiring 2, and the wiring such as a power supply through which a relatively large current flows may be constructed by overlapping the first wiring 2 and the second wiring 3. Thereby, when forming wiring for minute current, exposure and etching are performed using a thin conductive film, so that fine wiring can be formed.
また、大電流用配線は信頼性が高い充分な厚さに形成で
きる。Further, the wiring for large current can be formed to have a sufficient thickness with high reliability.
第２図（ａ）及び（ｂ）は本発明の第２実施例の平面図
、及びそのＢ−Ｂ線に沿う断面図である。FIGS. 2(a) and 2(b) are a plan view of a second embodiment of the present invention and a cross-sectional view thereof taken along line B-B.
この実施例では、第１配線２を形成した上で、微小電流
用配線の上に第１層間絶縁膜５を形成してこれを被覆し
ている。そして、全面に導体膜を形成しかつエツチング
して第１層間絶縁膜５が存在しない領域に第２配線３を
形成し、この領域では第１配線２と第２配線３を重ねた
厚い配線として形成している。そして、この上に第２層
間絶縁膜６を形成し、スルーホール７を通して第３配線
８を第２配線３に導通させている。なお、４は保護絶縁
膜である。In this embodiment, after forming the first wiring 2, a first interlayer insulating film 5 is formed on the minute current wiring to cover it. Then, a conductive film is formed on the entire surface and etched to form the second wiring 3 in the area where the first interlayer insulating film 5 does not exist, and in this area, the first wiring 2 and the second wiring 3 are overlapped to form a thick wiring. is forming. Then, a second interlayer insulating film 6 is formed on this, and the third wiring 8 is electrically connected to the second wiring 3 through the through hole 7. Note that 4 is a protective insulating film.
この実施例においても、微小電流用配線を第１配線２の
みで構成しているため、微細配線を容易に形成でき、一
方では大電流用配線を第１配線２と第２配線３とで充分
に厚く形成できる。Also in this embodiment, since the wiring for small current is composed of only the first wiring 2, fine wiring can be easily formed, while the wiring for large current can be formed by the first wiring 2 and the second wiring 3. Can be formed thickly.
なお、第１．第２．第３の各配線は、アルミニウム、高
融点金属、或いは多結晶シリコン等任意のもので構成で
きる。In addition, 1. Second. Each third wiring can be made of any material such as aluminum, high melting point metal, or polycrystalline silicon.
以上説明したように本発明は、一部の配線を薄い第１配
線で構成し、他の配線を第１配線と第２配線とを積層し
て構成しているので、第１配線を微細に形成して微小電
流用配線の微細化を実現するとともに、第１配線と第２
配線の積層により大電流用配線を充分厚く構成して信頼
性を向上させる。As explained above, in the present invention, some of the wirings are made up of thin first wirings, and other wirings are made up of stacked first wirings and second wirings, so that the first wirings can be made fine. In addition to realizing miniaturization of microcurrent wiring by forming
By stacking the wiring, the wiring for large currents can be made sufficiently thick to improve reliability.
第１図は本発明の第１実施例を示しており、同図（ａ）
は平面図、同図（ｂ）はＡ−Ａ線断面図、第２図は本発
明の第２実施例を示しており、同図（ａ）は平面図、同
図（ｂ）はＢ−Ｂ線断面図、第３図は従来構成を示して
おり、同図（ａ）は平面図、同図（ｂ）はＣ−Ｃ線断面
図である。
１・・・半導体チップ基板、２・・・第１配線、３・・
・第２配線、４・・・保護絶縁膜、５・・・第１層間絶
縁膜、６・・・第２層間絶縁膜、７・・・スルーホール
、８・・・第３配線、１１・・・半導体チップ基板、１
２・・・配線、１３・・・保護絶縁膜。
第
図
第２
図
（ａ）FIG. 1 shows a first embodiment of the present invention, and FIG.
2 is a plan view, FIG. 2(b) is a sectional view taken along the line A-A, and FIG. A sectional view taken along the line B and FIG. 3 show a conventional configuration, and FIG. 3(a) is a plan view, and FIG. 3(b) is a sectional view taken along the line C--C. DESCRIPTION OF SYMBOLS 1... Semiconductor chip board, 2... First wiring, 3...
- Second wiring, 4... Protective insulating film, 5... First interlayer insulating film, 6... Second interlayer insulating film, 7... Through hole, 8... Third wiring, 11.・・Semiconductor chip substrate, 1
2... Wiring, 13... Protective insulating film. Figure 2 (a)
Claims (1)
１配線上に選択的に重ねて被着した導体膜で形成した第
２配線とを備え、一部の配線を前記第１配線のみで構成
し、他の配線を第１配線と第２配線の積層構造で構成し
たことを特徴とする半導体集積回路装置。1. A first wiring formed of a thin conductive film on a substrate, and a second wiring formed of a conductive film selectively overlaid on the first wiring, and a part of the wiring is connected to the first wiring. 1. A semiconductor integrated circuit device comprising only wiring, and other wiring having a laminated structure of first wiring and second wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25625588A JPH02102535A (en) | 1988-10-12 | 1988-10-12 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25625588A JPH02102535A (en) | 1988-10-12 | 1988-10-12 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02102535A true JPH02102535A (en) | 1990-04-16 |
Family
ID=17290099
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25625588A Pending JPH02102535A (en) | 1988-10-12 | 1988-10-12 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02102535A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5363976A (en) * | 1976-11-19 | 1978-06-07 | Fujitsu Ltd | Semiconductor device |
| JPS564247A (en) * | 1979-06-25 | 1981-01-17 | Toshiba Corp | Wiring integrated at high degree |
-
1988
- 1988-10-12 JP JP25625588A patent/JPH02102535A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5363976A (en) * | 1976-11-19 | 1978-06-07 | Fujitsu Ltd | Semiconductor device |
| JPS564247A (en) * | 1979-06-25 | 1981-01-17 | Toshiba Corp | Wiring integrated at high degree |
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