JPH0185630U - - Google Patents
Info
- Publication number
- JPH0185630U JPH0185630U JP18174087U JP18174087U JPH0185630U JP H0185630 U JPH0185630 U JP H0185630U JP 18174087 U JP18174087 U JP 18174087U JP 18174087 U JP18174087 U JP 18174087U JP H0185630 U JPH0185630 U JP H0185630U
- Authority
- JP
- Japan
- Prior art keywords
- sampling period
- storage means
- input signals
- intelligent recorder
- storing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005070 sampling Methods 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 1
Landscapes
- Recording Measured Values (AREA)
Description
第１図は、この考案が実施されるインテリジエ
ントレコーダの回路ブロツク図、第２図は、同イ
ンテリジエントレコーダのサンプリング周期のプ
ログラミング設定動作を説明するためのフロー図
、第３図は、同インテリジエントレコーダのサン
プリング周期の変更処理を説明するためのフロー
図、第４図は、時間毎のサンプリング周期の設定
例を説明するための図、第５図は、サンプリング
周期の変更動作を説明するためのタイムチヤート
である。
３：Ａ／Ｄ変換器、４：ＣＰＵ、８：フロツピ
デイスクドライブ、１５：ＰＲＯＭ、１３：キー
ボード。
Fig. 1 is a circuit block diagram of an intelligent recorder in which this invention is implemented, Fig. 2 is a flow diagram for explaining the programming setting operation of the sampling period of the intelligent recorder, and Fig. 3 is a circuit diagram of the intelligent recorder. FIG. 4 is a flowchart for explaining the process of changing the sampling period of the Ent recorder, FIG. 4 is a diagram for explaining an example of setting the sampling period for each time, and FIG. 5 is a flow diagram for explaining the operation of changing the sampling period. This is a time chart. 3: A/D converter, 4: CPU, 8: floppy disk drive, 15: PROM, 13: keyboard.
Claims (1)
かつＡ／Ｄ変換器により、デジタル信号に変換し
て取込み、各入力信号を時間順次に記憶手段に記
憶するようにしたインテリジエントレコーダにお
いて、 各入力信号のサンプリング周期を、各入力信号
毎に、個別にプログラムして入力するプログラミ
ング設定手段と、前記設定された各入力信号毎の
サンプリング周期を記憶するサンプリング周期記
憶手段とを備え、前記各入力信号の記憶手段への
記憶を、サンプリング周期記憶手段に記憶される
サンプリング周期に基づいて行うようにしたこと
を特徴とするインテリジエントレコーダ。[Scope of claim for utility model registration] Sampling multiple analog input signals,
In the intelligent recorder, the input signals are converted into digital signals by an A/D converter, and each input signal is stored in a storage means in time sequence. A programming setting means for individually programming and inputting, and a sampling period storage means for storing a sampling period for each of the set input signals, and a sampling period storage means for storing each input signal in the storage means. An intelligent recorder is characterized in that the recording is performed based on a sampling period stored in an intelligent recorder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18174087U JPH0185630U (en) | 1987-11-27 | 1987-11-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18174087U JPH0185630U (en) | 1987-11-27 | 1987-11-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0185630U true JPH0185630U (en) | 1989-06-07 |
Family
ID=31473214
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18174087U Pending JPH0185630U (en) | 1987-11-27 | 1987-11-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0185630U (en) |
-
1987
- 1987-11-27 JP JP18174087U patent/JPH0185630U/ja active Pending
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