JPH0184449U - - Google Patents
Info
- Publication number
- JPH0184449U JPH0184449U JP1987180583U JP18058387U JPH0184449U JP H0184449 U JPH0184449 U JP H0184449U JP 1987180583 U JP1987180583 U JP 1987180583U JP 18058387 U JP18058387 U JP 18058387U JP H0184449 U JPH0184449 U JP H0184449U
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- lead
- shape
- semiconductor
- tip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
- H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987180583U JPH0184449U (enExample) | 1987-11-26 | 1987-11-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987180583U JPH0184449U (enExample) | 1987-11-26 | 1987-11-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0184449U true JPH0184449U (enExample) | 1989-06-05 |
Family
ID=31472097
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987180583U Pending JPH0184449U (enExample) | 1987-11-26 | 1987-11-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0184449U (enExample) |
-
1987
- 1987-11-26 JP JP1987180583U patent/JPH0184449U/ja active Pending