JPH0172719U - - Google Patents

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Publication number
JPH0172719U
JPH0172719U JP1987166769U JP16676987U JPH0172719U JP H0172719 U JPH0172719 U JP H0172719U JP 1987166769 U JP1987166769 U JP 1987166769U JP 16676987 U JP16676987 U JP 16676987U JP H0172719 U JPH0172719 U JP H0172719U
Authority
JP
Japan
Prior art keywords
decoder
bits
gain
resistance value
operational amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987166769U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987166769U priority Critical patent/JPH0172719U/ja
Publication of JPH0172719U publication Critical patent/JPH0172719U/ja
Pending legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図は本考案の実施例を示し、
第1図は主回路の回路図、第2図はクロスポイン
トスイツチのブロツク図、第3図は従来例の回路
図である。 0〜15……アナログスイツチ、21……デコ
ーダ、A……演算増幅器、R31,R41〜R
,R51〜R54……抵抗器、B〜B……
ビツト、X〜X,Y〜Y……母線。
1 and 2 show an embodiment of the present invention,
FIG. 1 is a circuit diagram of the main circuit, FIG. 2 is a block diagram of a cross-point switch, and FIG. 3 is a circuit diagram of a conventional example. 0 to 15...Analog switch, 21...Decoder, A...Operation amplifier, R31 , R41 to R4
3
, R51 to R54 ...Resistor, B0 to B3 ...
Bits, X0 to X3 , Y0 to Y3 ... Bus line.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 演算増幅器の帰還抵抗値を加減し、前記演算増
幅器の利得を変化させるレベル変換回路において
、複数ビツトからなる2進コードの信号を10進
数の信号へ変換するデコーダと、各々が前記複数
ビツトと対応する数のX,Y両母線およびこれら
の交差点を接続しかつ前記デコーダの出力により
駆動されるアナログスイツチからなるクロスポイ
ントスイツチと、前記アナログスイツチの接続に
したがい合成抵抗値が変化し利得を前記2進コー
ドに応じて定める互いに直列として接続された複
数の帰還用抵抗器とを備えたことを特徴とするレ
ベル変換回路。
A level conversion circuit that adjusts a feedback resistance value of an operational amplifier to change the gain of the operational amplifier includes a decoder that converts a binary code signal consisting of a plurality of bits into a decimal signal, each corresponding to the plurality of bits. A cross point switch consists of a number of X and Y bus lines and an analog switch connected to the intersections thereof and driven by the output of the decoder, and the combined resistance value changes according to the connection of the analog switch, and the gain is 1. A level conversion circuit comprising a plurality of feedback resistors connected in series with each other and determined according to a base code.
JP1987166769U 1987-11-02 1987-11-02 Pending JPH0172719U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987166769U JPH0172719U (en) 1987-11-02 1987-11-02

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987166769U JPH0172719U (en) 1987-11-02 1987-11-02

Publications (1)

Publication Number Publication Date
JPH0172719U true JPH0172719U (en) 1989-05-16

Family

ID=31454448

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987166769U Pending JPH0172719U (en) 1987-11-02 1987-11-02

Country Status (1)

Country Link
JP (1) JPH0172719U (en)

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