JPS63178911U - - Google Patents
Info
- Publication number
- JPS63178911U JPS63178911U JP6886587U JP6886587U JPS63178911U JP S63178911 U JPS63178911 U JP S63178911U JP 6886587 U JP6886587 U JP 6886587U JP 6886587 U JP6886587 U JP 6886587U JP S63178911 U JPS63178911 U JP S63178911U
- Authority
- JP
- Japan
- Prior art keywords
- level converter
- converter circuit
- operational amplifier
- binary code
- cross point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003321 amplification Effects 0.000 claims 1
- 238000003199 nucleic acid amplification method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Analogue/Digital Conversion (AREA)
- Control Of Amplification And Gain Control (AREA)
Description
第１図は本考案によるレベルコンバータ回路に
用いる演算増幅器による反転増幅回路の実施例を
示す回路図、第２図は本考案によるレベルコンバ
ータ回路に用いるクロスポイントスイツチの実施
例を示す構成図、第３図は従来のレベルコンバー
タ回路に用いる演算増幅器による反転増幅器を利
用した利得の切り替え回路の一例を示す回路図で
ある。
１１……演算増幅器（反転増幅器）、１２……
反転入力抵抗、１３，１４……帰還抵抗、１５，
１６……利得切り替え端子、２１……バイナリコ
ード入力、２２……４ｔｏ１６ｌｉｎｅデコーダ
、２３……１６ビツトラツチ、２４０，２４１〜
２４１５……アナログスイツチ、２５，２６……
アナログスイツチ端子。
1 is a circuit diagram showing an embodiment of an inverting amplifier circuit using an operational amplifier used in a level converter circuit according to the present invention; FIG. 2 is a block diagram showing an embodiment of a cross-point switch used in a level converter circuit according to the present invention; FIG. 3 is a circuit diagram showing an example of a gain switching circuit using an inverting amplifier using an operational amplifier used in a conventional level converter circuit. 11... operational amplifier (inverting amplifier), 12...
Inverting input resistance, 13, 14... Feedback resistance, 15,
16... Gain switching terminal, 21... Binary code input, 22... 4 to 16 line decoder, 23... 16 bit latch, 24 0 , 24 1 ~
24 15 ...Analog switch, 25, 26...
Analog switch terminal.
Claims (1)
ツチと４×４で配列されたアナログスイツチで構
成したクロスポイントスイツチと、演算増幅器に
よる反転増幅器を用いたレベルコンバータ回路を
有し、前記クロスポイントスイツチにバイナリー
コードを与え、このバイナリーコードの重みに比
例した増幅率あるいは減衰率を前記演算増幅器の
出力から得るようにしたことを特徴とするレベル
コンバータ回路。 It has a cross point switch composed of a 4 to 16 line decoder, a 16 bit latch, and analog switches arranged in a 4 x 4 arrangement, and a level converter circuit using an inverting amplifier using an operational amplifier.A binary code is given to the cross point switch, and this A level converter circuit characterized in that an amplification factor or an attenuation factor proportional to the weight of the binary code is obtained from the output of the operational amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6886587U JPS63178911U (en) | 1987-05-11 | 1987-05-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6886587U JPS63178911U (en) | 1987-05-11 | 1987-05-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63178911U true JPS63178911U (en) | 1988-11-18 |
Family
ID=30909073
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6886587U Pending JPS63178911U (en) | 1987-05-11 | 1987-05-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63178911U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8322513B2 (en) | 2005-08-31 | 2012-12-04 | F.R. Drake Company | Apparatus and method for loading food articles |
-
1987
- 1987-05-11 JP JP6886587U patent/JPS63178911U/ja active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8322513B2 (en) | 2005-08-31 | 2012-12-04 | F.R. Drake Company | Apparatus and method for loading food articles |
| US8434610B2 (en) | 2005-08-31 | 2013-05-07 | F.R. Drake Company | Apparatus and method for loading food articles |