JPH0157432B2 - - Google Patents
Info
- Publication number
- JPH0157432B2 JPH0157432B2 JP56145465A JP14546581A JPH0157432B2 JP H0157432 B2 JPH0157432 B2 JP H0157432B2 JP 56145465 A JP56145465 A JP 56145465A JP 14546581 A JP14546581 A JP 14546581A JP H0157432 B2 JPH0157432 B2 JP H0157432B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- inverter
- latch
- circuit
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000000295 complement effect Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 9
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 8
- 230000003213 activating effect Effects 0.000 description 3
- 101100508840 Daucus carota INV3 gene Proteins 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 102100036345 Calicin Human genes 0.000 description 1
- 101000714682 Homo sapiens Calicin Proteins 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/06—Address interface arrangements, e.g. address buffers
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Static Random-Access Memory (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56145465A JPS5848292A (ja) | 1981-09-17 | 1981-09-17 | アドレス・バツフア回路 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56145465A JPS5848292A (ja) | 1981-09-17 | 1981-09-17 | アドレス・バツフア回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5848292A JPS5848292A (ja) | 1983-03-22 |
JPH0157432B2 true JPH0157432B2 (de) | 1989-12-05 |
Family
ID=15385862
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56145465A Granted JPS5848292A (ja) | 1981-09-17 | 1981-09-17 | アドレス・バツフア回路 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5848292A (de) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4677593A (en) * | 1985-06-20 | 1987-06-30 | Thomson Components-Mostek Corp. | Low active-power address buffer |
JPH0289292A (ja) * | 1988-09-26 | 1990-03-29 | Toshiba Corp | 半導体メモリ |
JPH02105392A (ja) * | 1988-10-14 | 1990-04-17 | Nec Corp | 半導体メモリ装置 |
-
1981
- 1981-09-17 JP JP56145465A patent/JPS5848292A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS5848292A (ja) | 1983-03-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0326296B1 (de) | Datenflip-flop mit einer Datenhaltezeit gleich Null | |
US5087835A (en) | Positive edge triggered synchronized pulse generator | |
US6563357B1 (en) | Level converting latch | |
JPH05144273A (ja) | 半導体集積回路装置 | |
US5751176A (en) | Clock generator for generating complementary clock signals with minimal time differences | |
US20040150448A1 (en) | Clock controlled power-down state | |
GB2339502A (en) | Low skew pulse generators for double data rate synchronous DRAMs | |
US4617477A (en) | Symmetrical output complementary buffer | |
JPH10190416A (ja) | フリップフロップ回路 | |
JP3502116B2 (ja) | 単一ワイヤクロックを有する2段cmosラッチ回路 | |
US4606012A (en) | Sense amplifier | |
JPH0157432B2 (de) | ||
JPH1173775A (ja) | 半導体記憶装置の出力回路 | |
KR910005975B1 (ko) | 반도체 집적회로 | |
JPH0576120B2 (de) | ||
JPS6070817A (ja) | 論理回路 | |
JP3109986B2 (ja) | 信号遷移検出回路 | |
JPH0574854B2 (de) | ||
JP2000182375A (ja) | 半導体メモリ装置 | |
JPS622485B2 (de) | ||
JP2946960B2 (ja) | 半導体記憶装置 | |
JPH06236691A (ja) | 半導体記憶装置 | |
JPH09307409A (ja) | データ保持回路およびバッファ回路 | |
KR0164393B1 (ko) | 이씨엘 쇼트펄스 발생기를 이용한 어드레스 샘플링 회로 및 방법 | |
JP3231499B2 (ja) | 半導体集積回路 |