JPH0149068B2 - - Google Patents
Info
- Publication number
- JPH0149068B2 JPH0149068B2 JP58014257A JP1425783A JPH0149068B2 JP H0149068 B2 JPH0149068 B2 JP H0149068B2 JP 58014257 A JP58014257 A JP 58014257A JP 1425783 A JP1425783 A JP 1425783A JP H0149068 B2 JPH0149068 B2 JP H0149068B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- bit
- circuit
- period
- synchronization
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1407—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
- G11B20/1419—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Dc Digital Transmission (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58014257A JPS59140755A (ja) | 1983-01-31 | 1983-01-31 | バイフエ−ズマ−ク変調回路 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58014257A JPS59140755A (ja) | 1983-01-31 | 1983-01-31 | バイフエ−ズマ−ク変調回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59140755A JPS59140755A (ja) | 1984-08-13 |
JPH0149068B2 true JPH0149068B2 (enrdf_load_stackoverflow) | 1989-10-23 |
Family
ID=11856033
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58014257A Granted JPS59140755A (ja) | 1983-01-31 | 1983-01-31 | バイフエ−ズマ−ク変調回路 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59140755A (enrdf_load_stackoverflow) |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5732539B2 (enrdf_load_stackoverflow) * | 1974-09-20 | 1982-07-12 | ||
JPS5358709A (en) * | 1976-11-08 | 1978-05-26 | Nippon System Kogyo Kk | Synchronous word forming system for base band transmission |
JPS5814104B2 (ja) * | 1978-04-28 | 1983-03-17 | 株式会社東芝 | 情報伝送方式 |
-
1983
- 1983-01-31 JP JP58014257A patent/JPS59140755A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS59140755A (ja) | 1984-08-13 |
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