JPH0149068B2 - - Google Patents

Info

Publication number
JPH0149068B2
JPH0149068B2 JP58014257A JP1425783A JPH0149068B2 JP H0149068 B2 JPH0149068 B2 JP H0149068B2 JP 58014257 A JP58014257 A JP 58014257A JP 1425783 A JP1425783 A JP 1425783A JP H0149068 B2 JPH0149068 B2 JP H0149068B2
Authority
JP
Japan
Prior art keywords
signal
bit
circuit
period
synchronization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58014257A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59140755A (ja
Inventor
Tetsushi Itoi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
Original Assignee
NEC Home Electronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd filed Critical NEC Home Electronics Ltd
Priority to JP58014257A priority Critical patent/JPS59140755A/ja
Publication of JPS59140755A publication Critical patent/JPS59140755A/ja
Publication of JPH0149068B2 publication Critical patent/JPH0149068B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10Digital recording or reproducing
    • G11B20/14Digital recording or reproducing using self-clocking codes
    • G11B20/1403Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1407Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
    • G11B20/1419Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP58014257A 1983-01-31 1983-01-31 バイフエ−ズマ−ク変調回路 Granted JPS59140755A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58014257A JPS59140755A (ja) 1983-01-31 1983-01-31 バイフエ−ズマ−ク変調回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58014257A JPS59140755A (ja) 1983-01-31 1983-01-31 バイフエ−ズマ−ク変調回路

Publications (2)

Publication Number Publication Date
JPS59140755A JPS59140755A (ja) 1984-08-13
JPH0149068B2 true JPH0149068B2 (enrdf_load_stackoverflow) 1989-10-23

Family

ID=11856033

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58014257A Granted JPS59140755A (ja) 1983-01-31 1983-01-31 バイフエ−ズマ−ク変調回路

Country Status (1)

Country Link
JP (1) JPS59140755A (enrdf_load_stackoverflow)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5732539B2 (enrdf_load_stackoverflow) * 1974-09-20 1982-07-12
JPS5358709A (en) * 1976-11-08 1978-05-26 Nippon System Kogyo Kk Synchronous word forming system for base band transmission
JPS5814104B2 (ja) * 1978-04-28 1983-03-17 株式会社東芝 情報伝送方式

Also Published As

Publication number Publication date
JPS59140755A (ja) 1984-08-13

Similar Documents

Publication Publication Date Title
US4167028A (en) Method and an apparatus for time signal encoding/decoding
US4647828A (en) Servo system
US5142420A (en) Sampling frequency reproduction system
JP2919380B2 (ja) ディスク回転速度制御回路
JPH0149068B2 (enrdf_load_stackoverflow)
JPH0145789B2 (enrdf_load_stackoverflow)
JPS5943860B2 (ja) フレ−ム同期信号検出回路
JP3171205B2 (ja) 変調周波数検出回路
JPS60257616A (ja) パルス発生回路
JP2587556B2 (ja) クロック再生回路
JPH0527176B2 (enrdf_load_stackoverflow)
JP3091536B2 (ja) ビデオテープレコーダのフィールド判別回路
JPH0551986B2 (enrdf_load_stackoverflow)
JPS60261213A (ja) パルス発生回路
JP2693085B2 (ja) 信号のデューティ比識別回路
JPS6212585B2 (enrdf_load_stackoverflow)
JP2553072B2 (ja) 同期回路
JPS6158911B2 (enrdf_load_stackoverflow)
JPS63113841A (ja) 磁気テ−プの記録速度自動判別装置
JPH0230107B2 (ja) Jikikirokuyomitorihoshiki
JPS61147617A (ja) パルス信号の変調クロツク検出回路
JPS59140615A (ja) デイスク・プレ−ヤのクロツク再生回路
JPS6212584B2 (enrdf_load_stackoverflow)
JPH0467701B2 (enrdf_load_stackoverflow)
JPS59230354A (ja) パルス発生回路