JPH0139130B2 - - Google Patents

Info

Publication number
JPH0139130B2
JPH0139130B2 JP8612183A JP8612183A JPH0139130B2 JP H0139130 B2 JPH0139130 B2 JP H0139130B2 JP 8612183 A JP8612183 A JP 8612183A JP 8612183 A JP8612183 A JP 8612183A JP H0139130 B2 JPH0139130 B2 JP H0139130B2
Authority
JP
Japan
Prior art keywords
input
logic
output
signal
logic gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP8612183A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59211139A (ja
Inventor
Masaru Uya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP8612183A priority Critical patent/JPS59211139A/ja
Publication of JPS59211139A publication Critical patent/JPS59211139A/ja
Publication of JPH0139130B2 publication Critical patent/JPH0139130B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/5016—Half or full adders, i.e. basic adder cells for one denomination forming at least one of the output signals directly from the minterms of the input signals, i.e. with a minimum number of gate levels

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
JP8612183A 1983-05-16 1983-05-16 全加算器 Granted JPS59211139A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8612183A JPS59211139A (ja) 1983-05-16 1983-05-16 全加算器

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8612183A JPS59211139A (ja) 1983-05-16 1983-05-16 全加算器

Publications (2)

Publication Number Publication Date
JPS59211139A JPS59211139A (ja) 1984-11-29
JPH0139130B2 true JPH0139130B2 (fr) 1989-08-18

Family

ID=13877864

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8612183A Granted JPS59211139A (ja) 1983-05-16 1983-05-16 全加算器

Country Status (1)

Country Link
JP (1) JPS59211139A (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6123233A (ja) * 1984-07-11 1986-01-31 Nec Corp 演算数比較器
US4767949A (en) * 1987-05-01 1988-08-30 Rca Licensing Corporation Multibit digital threshold comparator

Also Published As

Publication number Publication date
JPS59211139A (ja) 1984-11-29

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