JPH01314331A - Multibit controller - Google Patents

Abstract

PURPOSE:To improve the processing ability by detecting plural processing modes of control information from a control register, selecting single processing modes in order from control information wherein the plural processing modes to be executed are predetermined, outputting the control information to an auxiliary register and controlling a switching circuit. CONSTITUTION:A plural-mode processing part 4 detects plural processing modes of the control information from the control register 1, selecting single modes in order from the control information wherein the processing modes to be executed are predetermined, and outputs the control information to the auxiliary register 3 and also controls the switching circuit 5. Namely, when the plural processing modes are specified, those plural processing modes are detected and the single processing modes are selected in order from the control information which contains the plural processing modes to be executed, and outputs them from the auxiliary register 3. This operation is repeated to perform the plural processing mode continuously. Consequently, the number of steps of a microprogram can be decreased, the load on the microprogram is reduced, and the processing ability is improved.

Description

[Detailed Description of the Invention] [Summary] Regarding a multi-bit control device that determines multiple processing orders of control information composed of multiple bits, by determining the processing order of multiple processing modes using hardware,
The purpose of the present invention is to provide a multi-bit control device that reduces the burden on microprograms, improves processing performance, and prevents malfunctions, and includes a control register that stores control information consisting of multiple bits; an auxiliary register for storing control information in which a processing mode is selected; a switching circuit for switching between the output of the auxiliary register and the output of the control register; and a plurality of processing modes for the control information from the control register to be detected and executed. The multi-mode processing section sequentially selects a single processing mode from control information in which a plurality of processing modes are predetermined, outputs the control information to the auxiliary register, and controls the switching circuit.

[Industrial Application Field] The present invention relates to a multi-bit control device that determines multiple processing orders of control information composed of multiple bits.

A data processing control device that has a control register that stores control information made up of multiple bits, and that determines the processing content by detecting that a specific bit is set in the control register, can perform multiple processing When control information specifying a mode is set, one of a plurality of processing modes is selected by the microprogram, and as soon as this is processed, another processing mode is selected and processed.

In this case, it is desirable to improve the processing capacity without increasing the burden on the microprogram.

[Prior Art] Generally, when control information specifying one specific processing mode is set in a control register by a microprogram, this specific processing mode is executed, and then the specific bit is reset after the processing is completed. Then, a bit designating another specific processing mode is set, and this processing mode is subsequently executed.

Next, when a plurality of processing modes are specified and the plurality of processing modes are to be executed continuously, the microprogram writes bit information specifying the processing mode of the processing number valve to be executed into the control register.

For example, using a 4-bit example, when specifying two processing modes such as ``roolJ'', first
Set the processing mode of lJ in the control register and then roo
olj was executed, and then the processing mode of [O○10J was set in the control register and roloJ was executed.

[Problems to be Solved by the Invention] As mentioned above, conventionally, when multiple processing modes are to be executed continuously, each of the processing modes for the multiple runs must be set in the control register using a microprogram. As a result, the number of steps in the microprogram increases.1. There was a problem in that the burden on the microprogram increased and processing performance could not be improved.

Furthermore, if a multiple processing mode other than the multiple processing mode that is predetermined to be executed is specified, malfunctions may occur.

The present invention has been made in view of these conventional problems, and uses hardware to determine the processing order of multiple processing modes, thereby reducing the burden on microprograms and improving processing performance. It is an object of the present invention to provide a multi-bit type WJ device which is capable of increasing the number of bits and preventing malfunctions.

[Means to solve the problem] FIG. 1 is a basic configuration diagram of the present invention.

In FIG. 1, 1 is a control register that stores control information made up of a plurality of bits, 3 is an auxiliary register that stores control information for which processing mode is selected, and 5 is the output of the auxiliary register 3 and the 111 control described above. A switching circuit 4 switches the output of the register 1, and detects a plurality of processing modes of control information from the control register 1, and sequentially selects a single processing mode from the back of the control information in which the plurality of processing modes to be executed are predetermined. It is a multi-mode processing section that selects and outputs the control information to the auxiliary register 3 and controls the switching circuit 5.

[Operation] When multiple processing modes are specified, the multiple processing modes are detected and a single processing mode to be executed is sequentially selected from control information in which multiple processing modes to be executed are stored in advance. Select and output from auxiliary register 3. By repeating this, a plurality of processing modes are executed continuously.

Therefore, the number of steps in the microprogram can be reduced, the burden on the microprogram can be reduced, and the processing capacity can be improved.

Further, even if a plurality of processing modes other than the stored control information of the plurality of processing modes are designated, the designation becomes invalid, and malfunctions can be prevented.

[Example] Embodiments of the present invention will be described below based on the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention.

First, to explain the configuration, in FIG. 2, 1 is a control register, and this control register 1 has a data signal line 2.
Control information consisting of a plurality of bits is stored through the . Note that the control information is written into the control register 1 by a microprogram.

Reference numeral 3 denotes an auxiliary register, and this auxiliary register 3 stores control information for a single processing mode whose processing order is determined by a multiple mode processing unit 4, which will be described later.

5 is a multiplexer that functions as a switching circuit, and this multiplexer 5 switches between the output of the control register 1 and the output of the auxiliary register 3 in response to a control signal output from the multi-mode processing unit 4 via the control line 6, and outputs control information. is sent to a processing target device (not shown) via the data output line 7.

4 is the plural mode processing section, and the plural mode processing section 4
are a full adder 8, an addition counter 9, a subtraction counter 10.
It is composed of a read-only memory (ROM>11), an OR circuit 12, an AND circuit 13, and a reset circuit 14.

The full adder 8 functions as a multi-bit detection circuit, detects the multi-bit of control information output from the control register 1, counts the number of bits, and sets the counted data to the subtraction counter 10 via the signal line 15. At the same time, the addition counter 9 and the subtraction counter 10 are notified via the signal line 16 that the multi-bit has been detected, and roughly the AND circuit 13 is notified via the signal line 17.

The addition counter 9 functions as an address generation section, and control information is input from the control register 1 to the addition counter 9, and a signal for adding address data is input from the subtraction counter 10 via a signal line 18. The addition counter 9 sends an address for selecting control information stored in the read-only memory 11 to the read-only memory 11 via a signal line 19.
Output to. Control information for a plurality of processing modes to be executed is written in advance in the read-only memory 11, and the read-only memory 11 selects a single processing mode among the plurality of processing modes according to the address from the addition counter 9. Control information is output to the auxiliary register 3. That is, control information for the single processing mode in which the processing order has been determined is output to the auxiliary register 3.

A signal notifying the completion of processing is input to the subtraction counter 10 via the signal line 20, and the subtraction counter 10 uses this signal to subtract the multi-bit number from the full adder 8, and at the same time subtracts the multi-bit number from the full adder 8 via the signal line 18. A signal for adding address data to the addition counter 9 is output. In addition, the subtraction counter 10
outputs the number set by the full adder 8 to the multi-pin 1 to the OR circuit 12.

The AND circuit 13 outputs a control signal to the multiplexer 5 via the control line 6 based on the output of the OR circuit 12 and the multi-bit detection signal from the full adder 8, and transfers the output of the multiplexer 5 from the control register 1 to the auxiliary register 3. Switch to output. When all processing is completed, the reset circuit 14 is activated by the output of the OR circuit 12, and the contents of the control register 1 and the auxiliary register 3 are reset via the signal line 21.

Next, the operation will be explained.

First, in a normal case where a plurality of processing modes are not designated, the output of the control register 1 is outputted from the data signal line 7 via the multiplexer 5 to a processing target device (not shown).

The full adder 8 does not detect the multi-bit control information from the control register 1, and the output of the AND circuit 13 becomes "O+t", so the multiplexer 5 does not select the output of the auxiliary register 3.

On the other hand, when multiple processing modes are specified, the full adder 8 detects multiple bits, counts the number of bits, sets the counted data in the subtraction counter 10, and adds the detected multiple bits. The counter 9 and the subtraction counter 10 are notified.

Control information is input from the control register 1 to the crimping counter 9, and the addition counter 9 outputs an address to the read-only memory 11. The read-only memory 11 selects a single processing mode from among the plurality of processing modes based on the address from the addition counter 9 and outputs the control information to the auxiliary register 3.

On the other hand, the multi-bit number set in the subtraction counter 10 is input to the OR circuit 12, and the output of this OR circuit 12 and the output of the full adder 8 are input to the AND circuit 13, so that the output of the AND circuit 13 is 1. '', the multiplexer 5 switches the output of the control register 1 to the output of the auxiliary register 3. Thus, the control information stored in the auxiliary register 3 is outputted via the data output line 7, and the processing mode is executed.

When the execution of this processing mode is completed, the subtraction counter 10 subtracts the set multi-bit number in response to the completion signal, and simultaneously outputs a signal for adding address data to the addition counter 9. Therefore, the address of the control information for the next processing mode to be executed is output from the addition counter 9, and the control information for the next processing mode to be executed is stored in the auxiliary register 3 from the continuation dedicated memory 11.

By repeating the above operation until the output of the subtraction counter 10 becomes "OIT", a plurality of processing modes are executed in sequence. When all processing is completed, the reset circuit 14
This resets the contents of the control register 1 and the auxiliary register 3, and at the same time, the output of the AND circuit 13 1101F switches the multiplexer 5 so that it can perform the normal single processing mode.

Therefore, when multiple processing modes are specified, the processing order of the multiple processing modes can be determined consecutively by hardware, which reduces the number of steps in the microprogram and reduces the burden on the microprogram. can. As a result, processing capacity can be improved.

In addition, since control information for multiple processing modes to be executed is stored in advance in the read-only memory 11, if multiple processing modes other than the stored control information are specified, this designation becomes invalid and malfunctions. can be prevented.

[Effects of the Invention] As described above, according to the present invention, when multiple processing modes are specified, it is possible to detect this and execute the multiple processing modes consecutively. The number of steps can be reduced, and the burden on the microprogram can be reduced. As a result, processing capacity can be improved.

Additionally, multiple processing modes to be executed are predetermined and stored, so even if a multiple processing mode other than these processing modes is specified, that specification will be invalidated and malfunctions can be prevented. can.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram of the present invention, and FIG. 2 is a block diagram showing an embodiment of the present invention. In the figure, 1... Control register, 2... Data signal line, 3... Auxiliary register, 4... Multiple mode processing section, 5... Multiplexer (switching circuit), 6... Control line , 7...Data output line, 8...Full adder, 9...Addition counter, 10...Subtraction counter, 11...Memory for continuous output, 12...OR circuit, 13... AND circuit, 14... circuit to reset l, 15-21... signal line. 1st se'' Wandering P register 1st 4zeta month. Aoi 4 Ku$〃Father 7 Fig. 1 Chizugoro Month 6-Disaster 7 and Yuri・''L without flock episode Fig. 2

Claims (1)

[Claims] A control register (1) that stores control information consisting of a plurality of bits, an auxiliary register (3) that stores control information in which a processing mode is selected, and an output of the auxiliary register (3) and the control register ( 1), a switching circuit (5) for switching the output of control register (1), and a switching circuit (5) that detects multiple processing modes of control information from the control register (1) and selects a single processing mode from among predetermined control information to be executed. Multi-bit control characterized by comprising: a multi-mode processing unit (4) that sequentially selects processing modes and outputs control information to the auxiliary register (3) and controls the switching circuit (5). Device.