JPS62216044A - Microcomputer - Google Patents
MicrocomputerInfo
- Publication number
- JPS62216044A JPS62216044A JP5995386A JP5995386A JPS62216044A JP S62216044 A JPS62216044 A JP S62216044A JP 5995386 A JP5995386 A JP 5995386A JP 5995386 A JP5995386 A JP 5995386A JP S62216044 A JPS62216044 A JP S62216044A
- Authority
- JP
- Japan
- Prior art keywords
- interrupt
- interruption
- address
- circuit
- addresses
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 5
- 240000002853 Nelumbo nucifera Species 0.000 description 1
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 1
- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はマイクロコンピュータに関し、特に複数の割込
みアドレスを選択できる割込み機能に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer, and particularly to an interrupt function that allows selection of a plurality of interrupt addresses.
従来、マイクロコンピユータの割υ込み機能は。 Conventionally, the interrupt function of microcomputers was
ある割込みリクエストが発生した場合、その割り込みリ
クエストに対して一義的に決められたプログラムのアド
レスに割込めるというものであった。When a certain interrupt request occurs, the program can be interrupted at a program address uniquely determined for that interrupt request.
上述した従来のマイクロコンピュータは、内蔵するそれ
ぞれの種類、レベルの割込みに対し1割込むプログラム
のアドレス(割込みアドレス)が1つづつ決められてい
る。すなわち1つの割込みリクエストによって1割込め
るアドレスは1つしかないので、複数の割込みアドレス
を選択し割込むことが基本的にできないという欠点があ
る。In the conventional microcomputer described above, one interrupt program address (interrupt address) is determined for each built-in interrupt type and level. That is, since there is only one address that can be interrupted by one interrupt request, there is a drawback that it is basically impossible to select and interrupt multiple interrupt addresses.
本発明のマイクロコンビエータは、割込みリクエストを
検出する割込み検出回路と、外部から入力aれる割込み
アドレス選択信号によって複数の割込みアドレスを選択
する割込みアドレス選択回路と、複数の割込みアドレス
を格納し、前述の割込みアドレス選択回路によって指定
される割込みアドレスを発生する割込みアドレス・テー
ブルとを有することを特徴とする。The micro combinator of the present invention includes an interrupt detection circuit that detects an interrupt request, an interrupt address selection circuit that selects a plurality of interrupt addresses based on an interrupt address selection signal input from the outside, and a plurality of interrupt addresses that are stored. and an interrupt address table that generates an interrupt address specified by the interrupt address selection circuit of the interrupt address selection circuit.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例である。割込み入力端子1か
ら入力された割込み信号は、割込み検出回路2によって
検出される。割込み検出回路によって検出された割込み
信号(割込リクエスト)は割込みアドレス選択回路3に
送られる。割込みアドレス選択回路3における割込みア
ドレスの選択は、割込みアドレス選択信号入力端子4か
ら入力される信号によって行なわれる。割込みアドレス
を格納した割込みアドレス・テーブル5は、割込みアド
レス選択回路3により指定されたテーブル・データすな
わち割込みアドレスを発生させ、内部バス5に転送する
。このようにしである一つの割込みリクエストであって
も、複数の割込みアドレスを選択することができる。FIG. 1 shows an embodiment of the present invention. An interrupt signal input from the interrupt input terminal 1 is detected by the interrupt detection circuit 2. The interrupt signal (interrupt request) detected by the interrupt detection circuit is sent to the interrupt address selection circuit 3. Selection of an interrupt address in the interrupt address selection circuit 3 is performed by a signal inputted from an interrupt address selection signal input terminal 4. The interrupt address table 5 storing interrupt addresses generates table data, ie, interrupt addresses, specified by the interrupt address selection circuit 3 and transfers them to the internal bus 5. In this way, multiple interrupt addresses can be selected even for a single interrupt request.
以上説明したように本発明は1割込みアドレスを外部か
ら制御できるようにすることにより、複数の割込みアド
レスを一つの割込みリクエストで選択できるので、よう
複雑なプログラム制御が可能であるという効果がある。As explained above, the present invention has the advantage that by allowing one interrupt address to be controlled from the outside, multiple interrupt addresses can be selected with a single interrupt request, making it possible to perform complex program control.
第1図は本発明の一実施例のブロック図でおる。
1・・・・・・割込み入力端子、2・・・・・・割込み
検出回路。
3・・・・・・ai込みアドレス選択回路、4・・・・
・・割込みアドレス選択信号入力端子、5・・・・・・
割込みアドレス・テーブル、6・・・・・・内部ハス。
代理人 弁理士 内 原 晋5.;ゞ′〜;)\
・#l
曳・−。。FIG. 1 is a block diagram of one embodiment of the present invention. 1...Interrupt input terminal, 2...Interrupt detection circuit. 3...Address selection circuit including AI, 4...
...Interrupt address selection signal input terminal, 5...
Interrupt address table, 6... Internal lotus. Agent: Susumu Uchihara, patent attorney 5. ;ゞ′〜;)\
・#l Hiki・-. .
Claims (1)
ら入力される割込みアドレス選択信号によって複数の割
込みアドレスを選択する割込みアドレス選択回路と、複
数の割込みアドレスを格納し前記割込みアドレス選択回
路によって指定される割込みアドレスを発生する割込み
アドレス・テーブルとを有することを特徴とするマイク
ロコンピュータ。An interrupt detection circuit that detects an interrupt request, an interrupt address selection circuit that selects multiple interrupt addresses based on an externally input interrupt address selection signal, and an interrupt that stores multiple interrupt addresses and is specified by the interrupt address selection circuit. A microcomputer comprising an interrupt address table for generating addresses.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5995386A JPS62216044A (en) | 1986-03-17 | 1986-03-17 | Microcomputer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5995386A JPS62216044A (en) | 1986-03-17 | 1986-03-17 | Microcomputer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62216044A true JPS62216044A (en) | 1987-09-22 |
Family
ID=13128016
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5995386A Pending JPS62216044A (en) | 1986-03-17 | 1986-03-17 | Microcomputer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62216044A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0335326A (en) * | 1989-06-30 | 1991-02-15 | Mitsubishi Electric Corp | Microprocessor |
-
1986
- 1986-03-17 JP JP5995386A patent/JPS62216044A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0335326A (en) * | 1989-06-30 | 1991-02-15 | Mitsubishi Electric Corp | Microprocessor |
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