JPS61177556A - Memory switching circuit - Google Patents

Abstract

PURPOSE:To save address space and to handle a large amount of data by accessing memory groups of all cards with common address. CONSTITUTION:When data is sent in from an external controller through a data bus 6 and an address bus 5, address data are inputted to both changeover number registers 8 and changeover number register 9 for extension of cards 4a-4n to detect the coincidence of each part. Then, changeover control parts 12 send out selection signals of memory groups 1a-1n to respective memory groups 1a-1n. Further, while an outward acknowledge signal is returned from the resending part 13 of the card 4a, the state wherein the internal memory groups 1a-1n of this card are selected is stored and operation is performed to subsequent access from the external controller. Then, when another change over number is sent from the data bus 6 newly, the sending part 13 is set at this stage and all the card 1a-1n are held in readiness to accept access.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory switching circuit that is used in information processing devices and the like and is capable of handling large amounts of data.

[Conventional technology]

Conventionally, there was a memory switching circuit of this type as shown in FIG. 2. In FIG. This is a register to keep the data. Similarly, each of 4a to 4n is the memory group 1a#lbt.
This is a card that includes hardware such as ~In, a switching control section 2, and a register 3. Further, 5 is an address bus, 6 is a data bus, and 7 is a control signal group.

Next, the operation will be explained. When data is sent from an external controller (not shown) to, for example, the card 4a via the data bus 6 and address bus 5, if the addresses match in the switching number register 3 in the card 4a, then data is stored in the register 3 as a switching number, and the switching control section 2 sends out a selection signal for selecting the memory groups 1a to 1n corresponding to the switching number.

After that, if the external controller (not shown) sends out the memory address corresponding to this card 4a,
Data is accessed to the corresponding memory at the corresponding address in the memory group 1a, for example.

[Problem that the invention seeks to solve]

Since the conventional memory switching circuit is configured as described above, when there are multiple cards 4a to 4n, the address for the register 3 and the address for the memory groups 1a to 1n are changed for each card 4a to 4a. There was a problem that if the address space of the external controller was small and the number of cards 4a to 4n was increased, the address space would inevitably be exceeded, making it impossible to handle large amounts of data. .

This invention was made to solve the above-mentioned problems, and it saves address space by making the addresses of register 3 and memory group 1&~1n a common address for all cards 4&~4n so that they can be accessed. The purpose of this invention is to provide a memory switching circuit that can effectively utilize the address space.

[Means for solving problems]

The memory switching device according to the present invention has a common address for memory groups in all cards connected to a data bus and an address bus, and a register for inputting and storing data from the address data bus and a register for storing data from the data bus, and a register for inputting and storing data from the address bus and the data bus. [Operation] The memory switching circuit according to the present invention is configured to select a memory group in the own card by providing a coincidence detection section for detecting a match between the card number of the card and the own card number. By accessing the addresses of the memory group of the card as a common address, the address space is saved and it becomes possible to handle a large amount of data. [Embodiment] An embodiment of the present invention will be described below with reference to the drawings. W.J.
In Figure 1, 1 a ~ I n s 4 a ~ 4 n
-, 5e 6 s 7 are the same as the same reference numerals in FIG.

8 is a switching number register, 9 is an expansion switching number register, and olO is a register corresponding to each card number 4m to 4a. olO is a card number setting section for setting a card number unique to each card 4a to 4a. 11 is a match detection unit that detects a card number match between the expansion switching number register 9 and the card number setting unit 10, 12 is a switching control unit, and 13 is a card number that is determined to be valid by this switching control unit 12. This is a return unit that not only sends back a signal of acceptance to an external controller (not shown) in response to the received card but also remembers that its own card 4& is currently selected.

Next, the operation will be explained. When data is sent from an external controller (not shown) via the data bus 6 and address bus 5, first the switching number register 8 of the cards 4a to 4n and the expansion switching Address bus data is input to both number registers 9, and matching is detected for each part. At this time, the data bus 6 sent at the same time
Since the above data includes data including the card numbers 4a to 4a, only one card among the cards 4a to 4n which received the card number from the card number setting section 10 and matched in the match detection section 11 is sent. be entitled to access. The other cards 4a to 4n give up their access rights at this stage.

Thereafter, the switching control unit 12 sends selection signals for the memory groups 1a to In to each memory group l&~I in accordance with the above-mentioned coincidence.
This card also sends a 7-fold signal to the outside.
At the same time as the return unit 13 of the card a stores that the internal memory groups 1a to 1n of the own card have been selected, the card operates against subsequent access from an external controller (not shown). After that, if another switching number is sent over the data bus 6, the return unit 13 is reset at this stage and all the cards 1a-In are returned to a state where they can accept access. Their full power - Do 1a~1
Cards 4a to 4 whose switching numbers match the selection among n
n will repeat the same operation as above again.

In the above embodiment, the case of memory switching has been described, but the same functions can be used and the same effects can be achieved even when selecting other peripheral devices.

〔Effect of the invention〕

As described above, according to the present invention, since the switching mechanism is configured so that each card can always be accessed using a common address, a large amount of data can be easily used even in a controller with a small address space, and the range of use of the controller can be expanded. It has the effect of obtaining something that is possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a memory switching circuit showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional memory switching circuit. In the figure, la to 1n are memory groups, 2 is a switching control unit, 4a to 4n are cards, 5 is an address bus, 6 is a data bus, 8 is a switching number register (register),
9 is an expansion switching number register (register), 11 is a coincidence detection section, and 12 is a switching control section. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] A plurality of data buses and an address bus are connected to each other, and data is input and stored from an external controller via these data buses and address buses, and a selection signal is output from a switching control unit to a plurality of memory groups. In a memory switching circuit comprising a plurality of cards for accessing the data to a memory group, an address of the memory group possessed by all the cards is used as a common address, and a register for inputting and storing address data in each of the cards; , each card is provided with a match detection unit that detects a match between the card number from this register and its own card number, and when the card number and its own card number match, the switching control unit sends the A memory switching circuit characterized in that it sends back an acknowledgment signal to an external controller and also selects a memory group within its own card.