JPH04281521A - Parallel sort device - Google Patents

Abstract

PURPOSE:To output data after rearranging the data in a prescribed order without increasing a buffer capacity, even when plural processor elements having the same data are present. CONSTITUTION:Key data stored in memories 201-241 of each processor element 200-240 are successively transmitted to a global bus 260 by the control of transmitting timing counters 204-244. Then, the transmitted data are compared with the data stored in the memories of each processor element by comparator circuits 203-243, and the compared result is counted by compared result counters 204-244. Then, the number of the data transmitted to the global bus is counted by the transmitting timing counters 205-245, and whether or not the compared result is counted by the compared result counters 204-244 is controlled when the compared result is an equal one, based on the counted result of the transmitting timing counters. A also, the key data and record data stored in the memories of each processor element are outputted in the prescribed order, based on the count values of the compared result counters 204-244.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel sorting device having a multiprocessor configuration in which a plurality of processor elements and a plurality of memories respectively connected to the plurality of processor elements are connected by a global bus.

0002

2. Description of the Related Art In a system in which data is distributed and stored in a plurality of modules, it is necessary to sort the keys of the stored data in ascending order (descending order) and outputting the data to the outside.

[0003] Several algorithms for sorting processing have been proposed, one of which is the parallel counting sorting method [
Yasuura, Takagi: “High-speed sorting circuit using parallel counting sort”, IEICE Transactions” 82/2, Vol. J65-D
, No. 2, pp. 179-186 (1982)]. The counting sorting method, which is the basis of parallel counting sorting, consists of two processes: ranking processing and rearranging processing.

[0004] Ranking process: The ranking of each key data (a part of record data) is determined.

[0005] Sorting process: Record data is sorted based on the results of the ranking process.

[0006] To explain the ranking process, the modules that make up the system count how many pieces of key data smaller (larger) than the key data it owns are in other modules, and based on the counted number. to determine the ranking. On the other hand, regarding sorting processing, key data is transmitted according to arbitrary rules (for example, the order of addresses assigned to each module), and the received data is sorted based on the ranking obtained by ranking processing. A method of sorting is used. Parallel count sorting is a method in which each module executes the above ranking process in parallel.

However, in the parallel counting sort proposed by Yasuura et al., the key data and record data are sent out from the module according to the input order of the key data rather than the ascending order (descending order) of the key data. In order to obtain the recorded record data, it is necessary to add a function for sorting key data to the management module (which has the function of managing all modules), or a method for the management module to poll the modules. . The former method has a problem in that the buffer capacity becomes large, and the latter method has a problem in that the execution time for sorting increases by the time taken for polling processing.

In order to solve this problem, in a multiprocessor in which a plurality of processor elements are bus-coupled, a register, an addition circuit, and a comparison circuit are added to each processor element, and a buffer for rearrangement and a rearrangement processing are added. We are currently applying for a patent for parallel counting sort that does not require time.

However, the above-mentioned patent does not assume a situation in which the same key data exists in a plurality of processor elements, and therefore there is a problem regarding transmission control of key data and record data. The problems of the prior art will be specifically explained below.

FIG. 4 shows the conventional parallel counting sort process when the same key data exists in multiple processors.
Explain using. Memory 101, 111, 121, 1
31 and 141, respectively.
, 110, 120, 130, 140 and a control processor 150 that performs interface control with an external information processing device (host) are connected via a global bus 160. Parallel counting sort is executed. shall be Processor elements 100, 110, 1
Memory 10 connected to 20, 130, 140, respectively
1, 111, 121, 131, and 141 store two items, a key (key data) and a record (record data), as a pair at each address, and the processor element 100
Address 1 of the memory 101 of the processor element 110 contains the key 456, record B, and address 1 of the memory 111 of the processor element 110.
has key 123 and record A, and address 1 of memory 121 of processor element 120 has key 789 and record E.
, a key 456 and a record C are stored at address 1 of the memory 131 of the processor element 130, and a key 456 and a record D are stored at address 1 of the memory 141 of the processor 140, respectively.

When an ascending sort instruction request is sent from an external information processing device (host) to the processor elements 100 , 110 , 120 , 130 , 140 via the control processor 150 and the global bus 160 , the processor element 100
, 110, 120, 130, 140 are memories 101, 1
Access the key data stored in address 1 of 11, 121, 131, 141 and register 102, 1
12, 122, 132, and 142, respectively, and then transmit timing counters 104, 114, and 124 with processor addresses given to each processor element.
, 134, 144 [Here, to simplify the explanation, the processor address of processor element 100 is 0, and the processor address of processor element 110 is 1.
, the processor address of processor element 120 is 2, the processor address of processor element 130 is 3, and the processor address of processor element 140 is 4]. Processor elements 100, 110, 120, 130,
140 is a timing counter 104, 114, 124, 134, 14 for transmitting the number of data on the global bus 160.
4, and the key data held in its own register is sequentially transmitted to the global bus 160 from the processor element whose counter value becomes 0.

In FIG. 4, since the value of the transmission timing counter 104 of the processor element 100 becomes 0 first,
The processor element 100 transmits the key data 456 held in the register 102 to other processor elements 11.
0, 120, 130, 140 are magnitude comparison circuits 115, 125, 135, 145 which receive the key data and compare the key data held in the register with the received key data 456.
If the held key is larger than the received key data, the comparison result counters 113 and 123
, 133, and 143 are updated by +1. Thereafter, key data is transmitted in the order of processor elements 110, 120, 130, 140, and comparison result counters 103, 113
, 123, 133, and 143 are also updated. The above processing results, comparison result counters 103, 113, 123,
The values of 133 and 143 are 1, 0, 4, 1, and 1, respectively, and the values are sent to the transmission timing counters 104, 114,
Set to 124, 134, 144. Further, the processor elements 100, 110, 120, 130, 140 set the key data and record data at address 1 in the registers 102, 112, 122, 132, 142. FIG. 4 is a diagram showing the results of the above processing.

Next, processor elements 100, 110, 1
20, 130, 140 are transmission timing counters 104, 114, 124 that measure the number of data on the global bus 160.
, 134, 144, and when the counter value reaches 0, the transmitting circuits 106, 116,
126, 136, 146 are registers 102, 112, 1
The key data and record data held in 22, 132, and 142 are transmitted to the global bus 160, but the processor element whose transmission timing counter value is not 0 continues counting down until the transmission timing counter value becomes 0. In FIG. 4, first, the counter value of the transmission timing counter 114 of the processor element 110 becomes 0, so the key data 123 and record data A held in the register 112 are transmitted to the global bus 160. The next processor elements whose transmission timing counter value becomes 0 are 100, 130, and 140.
Since each processor element attempts to transmit key data and record data at the same time, there is a conflict in the transmission order.

[0014]

[Problems to be Solved by the Invention] As mentioned above, in parallel counting sort processing, the value of the transmission timing counter is 0.
If there are a plurality of processor elements having the same key data, there is a problem that the transmission order conflicts between the plurality of processor elements.

[0015] In addition, as a method for avoiding such conflicts, a means for comparing the identifiers (processor addresses) of processor elements having the same key between processor elements, a counter for counting the result, and a means for comparing the result of the counter at the time of transmission are provided. One possibility is to add a counter to each processor element to count down the value, but this method requires adding a lot of hardware to the processor element.
The problem is that it is uneconomical.

The present invention has been made in view of the above, and
The objective is to create a parallel sorting device that sorts and outputs data in a predetermined order without increasing the buffer capacity for sorting even when there are multiple processor elements that have the same data. It is about providing.

[0017]

[Means for Solving the Problems] In order to achieve the above object, the parallel sorting device of the present invention provides a parallel sorting device in which a plurality of processor elements each having a memory are stored in the memory from a multiprocessor system connected via a common bus. A parallel sorting device that rearranges and outputs data stored in a predetermined order in a predetermined order, and each processor element includes a sending control unit that sequentially sends data stored in its own memory to a common bus in a predetermined order; a comparison means for comparing the data sent to the common bus by the sending control means with data stored in its own memory; a comparison result counting means for counting the results of the comparison; and sending the data to the common bus under the control of the sending control means. a data number counting means for counting the number of data that has been compared; and a data number counting means for counting whether or not the comparison result of the comparison means is counted by the comparison result counting means when the comparison results by the comparison means are equal. The gist of the present invention is to have a control means for controlling based on the result, and an output control means for outputting data stored in the memory of each processor element in a predetermined order based on the count value of the comparison result counting means. .

[0018]

[Operation] The parallel sorting device of the present invention sequentially sends the data stored in the memory of each processor element to the common bus in a predetermined order, and combines this output data with the data stored in the memory of each processor element. The comparison result is counted by a comparison result counting means, and the number of data sent to the common bus is counted by a data number counting means, and if the comparison results are equal, the comparison result is used as the comparison result. Controlling whether or not to count by the counting means based on the count result of the data number counting means, and sorting the data stored in the memory of each processor element in a predetermined order based on the count value of the comparison result counting means. Output.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the drawings.

FIG. 1 is an overall configuration diagram of a parallel processor configuration to which a parallel sorting device according to an embodiment of the present invention is applied. In the figure, 250 is a control processor that controls the interface between the parallel processor and an external processing device (host); 200, 210, 220, 230, 240;
is a processor element, 260 is a processor element 200,2
This is a global bus that connects 10, 220, 230, and 240.

FIG. 2 shows each processor element 200, 210
, 220, 230, 240 in detail. FIG. 2 depicts processor element 200 since each processor element is similarly configured. Note that each processor element 200, 210, 2
20, 230, and 240 have the same components as shown in FIG. 2, but in FIG. ing.

In FIG. 2, 201 is a memory, 202 is a register for registering key data read from the memory,
203 is a comparison circuit that compares the contents of the register 302 and the key data sent from the global bus; 204 is a comparison result counter that performs +1 addition updating according to the result of the comparison circuit 203 and instructions from the counter control circuit 207; 205 is a global A transmission timing counter that counts the number of data on the bus, 206 is a transmission timing counter 205
A transmitting circuit 207 instructs to transmit the data held in the register 202 based on the result of , and a transmitting circuit 207 includes the same key data held in the registers of other processor elements if the value of the sending timing counter 205 is greater than 0. The key data smaller than the key data held in the register 202 is counted, and if the value of the transmission timing counter 205 is 0 or less, only the key data smaller than the key data held in the register 202 is counted. This is a counter control circuit that issues an instruction to the comparison result counter 204 through the comparison circuit 203 to target the comparison result.

Next, the operation of the parallel sorting device constructed as above will be explained.

The external information processing device (host) transmits an ascending sort instruction request to the control processor 250, and the control processor 250 receives the instruction and sends all processor elements 200, 210,
220, 230, 240. Processor element 2
00, 210, 220, 230, 240 receive the relevant instruction from the control processor 250, and then the memories 201, 2
Read access is made to the key data at address 1 of 11, 221, 231, 241, and the key data corresponding to the instruction is stored in registers 202, 212, 222, 2.
32,242. This processing is performed simultaneously by each processor element 200, 210, 220, 230, and 240. That is, as a result of this processing, the register 20
2 stores key data 456, register 212 stores key data 123, register 222 stores key data 789, register 232 stores key data 456, and register 242 stores key data 456, respectively.

Processor elements 200, 210, 220,
230, 240 are other processor elements 200, 210,
Global bus 260 for 220, 230, 240
When transmitting key data via the processor element 2
00, 210, 220, 230, 240 are transmission timing counters 204, 21 that transmit identifiers (processor addresses) assigned in advance to each processor element.
4,224,234,244, and the transmission timing counters 204, 214, 224, 234, 244 count down the value set in the counter according to the number of data on the global bus 260, and when the counter value is 0,
When , registers 202, 212, 222, 232
, 242 is transferred to the global bus 2.
60 [Here, it is assumed that the data is transmitted in the order of processor element 200, processor element 210, processor element 220, processor element 230, and processor element 240].

First, the receiving processor element 210
, 220, 230, 240 are the sending processor elements 2
The comparison circuits 213, 223, 233, 243 receive the key data 456 sent from the register 212,
The key data registered in 222, 232, and 242 is compared with the received key data 456. register 21
Since the key data 123 registered in register 222 is smaller than the received key data 456, the value of the comparison result counter 214 is not updated, but the key data 789 registered in the register 222 is larger than the received key data 456, so the value of the comparison result counter The control circuit 227 instructs the comparison result counter 224 to update by +1. Also, registers 232, 2
42 holds the same key data as the received key data 456, but since the values of the transmission timing counters 235 and 245 are 2 and 3, respectively, the counter control circuits 237 and 2
47 instructs the comparison result counters 234 and 244 to be updated by +1.

In the next data transmission, processor element 210
Since the value of the transmission timing counter 215 becomes 0,
Key data 123 held in register 212 is transmitted to global bus 260. processor element 20
0, the value of the transmission timing counter 205 is -1, but the key data 45 held by the register 202
6 is larger than the received key data 123, the counter control circuit 207 instructs the comparison result counter 204 to update by +1. Additionally, processor elements 220, 230,
Since the key data held by the registers 222, 232, 242 of 240 are all larger than the received key data 123, the counter control circuits 227, 237, 247 also instruct the comparison result counters 224, 234, 244 to update by +1. .

Thereafter, the transmission timing counter 224,2
The key data held in the registers is transmitted to the processor elements 220 and 2 in accordance with the order in which the values of 34 and 244 become 0.
30, 240, and other processor elements 200, 210, 220, 230, 200, 210, 220, 230,
240 transmission timing counters 203, 213, 22
Updates of 3,233,243 are also executed. As a result of the completion of the processing described on the left, the comparison result counters 204, 214, 22
The values of 4,234,244 are updated to 1, 0, 4, 2, and 3, respectively. Next, processor elements 200, 210, 22
0, 230, 240 are the transmission timing counter 205,
After resetting the values of 215, 225, 235, and 245 to 0, the comparison result counters 204, 214, 224, and 2
The final result of 34,244 is sent to the timing counter 20.
5, 215, 225, 235, and 245, and key data and record data are set in registers 202, 212, 222, 232, and 242. FIG. 2 is an overall system diagram showing the above processing results.

Next, the operation when each processor element starts transmitting record data and key data from the state shown in FIG. 1 will be specifically explained using FIG. 3. Data transmission by a processor element begins when a transmission timing counter counts down the number of data on the global bus.

Note that in FIG. 3, each processor element 2
00, 210, 220, 230, 240, the meaning in parentheses () indicating the internal state of each processor including the initial state or in square brackets [] indicating the transmission data is (K, L, M ) and [K,L,M], then K
indicates key data, L indicates record data, and M indicates the value of the transmission timing counter.

In FIG. 3, the first data is transmitted in order I, and the processor element begins counting down the number of data. First, processor elements 200, 220, 23
0 and 240 are updated to 0, 3, 1, and 2, respectively, since the values of the transmission timing counters before updating are 1, 4, 2, and 3, respectively, but the key data and record data are not transmitted, and the processor element 210 Since the initial value of the transmission timing counter is 0, the transmission circuit 216 issues a data transmission instruction and first transmits the key data 123 and record data A onto the global bus.

In order II, when the second data is transmitted, the processor element 200 whose transmission timing counter value is 0 transmits the key data 456 and record data B to the global bus. Hereafter, in order III,
The processor element 230 sequentially transmits key data 456 and record data C, in order IV the processor element 240 transmits key data 456 and record data D, and in order V the processor element 220 sequentially transmits key data 789 and record data E on the global bus. do. The process of updating the transmission timing counter in each order is the same as in order I.

The control processor controls each processor element 200, 210, 220, 230, 24 in the course of the above processing.
Data sent from 0 through the global bus (
By sequentially receiving key data, record data), data containing the same key data can be obtained in a stream format in sorted order.

[0034]

[Effects of the Invention] As explained above, according to the present invention,
The data stored in the memory of each processor element is sequentially sent to the common bus in a predetermined order, the output data is compared with the data stored in the memory of each processor element, and the comparison result is used as the comparison result. At the same time as counting by the counting means, the number of data sent to the common bus is counted by the data number counting means, and if the comparison results are equal, the data determines whether or not the comparison result is to be counted by the comparison result counting means. The control is performed based on the counting result of the comparison result counting means, and the data stored in the memory of each processor element is output in a predetermined order based on the counted value of the comparison result counting means, so that processors having the same data Even if there are multiple elements, they are accurately sent in a predetermined order without conflict based on the result of counting the number of sent data, and there is no need for a buffer for rearranging the data, making it more economical. be able to.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of a multiprocessor system to which a parallel sorting device according to an embodiment of the present invention is applied.

FIG. 2 is a block diagram showing the internal configuration of a processor element used in the embodiment of FIG. 1;

FIG. 3 is an explanatory diagram showing the order in which data is transmitted between a plurality of processor elements when the same key data exists in a plurality of processor elements in the parallel sorting device shown in FIG. 1;

FIG. 4 is an overall configuration diagram of a multiprocessor that executes conventional parallel counting sort.

[Explanation of symbols]

200, 210, 220, 230, 240 Processor elements 201-241 Memories 202-242 Registers 203-243 Comparison circuits 204-244 Comparison result counters 205-245 Transmission timing counters 206-2
46 Transmission circuit 207-247 Counter control circuit

Claims (1)

[Claims] 1. A parallel sorting device that sorts and outputs data stored in each memory in a predetermined order from a multiprocessor system in which a plurality of processor elements each having a memory are connected via a common bus. , each processor element includes a transmission control means for sequentially transmitting data stored in its own memory to a common bus in a predetermined order, and a transmission control means for transmitting data stored in its own memory to the common bus. a comparison means for comparing the data, a comparison result counting means for counting the comparison results, a data number counting means for counting the number of data sent to the common bus under the control of the sending control means, and a comparison by the comparison means. control means for controlling whether or not the comparison result of the comparison means is counted by the comparison result counting means when the results are equal, based on the count result of the data number counting means; 1. A parallel sorting device comprising: output control means for outputting data stored in the memory of each processor element in a predetermined order based on the output control means.