JPH04247548A - Parallel sorter - Google Patents

Abstract

PURPOSE:To economically execute rearrangement in comparatively short processing time. CONSTITUTION:Data stored in respective memories 201, 211 and 221 are respectively successively transmitted to a global bus 250, these respective data are received by respective processor elements 200,210 and 220, and size comparator circuits 205, 215 and 225 compare the sizes of these received data with those of data stored in the respective memories 201, 211 and 221. These compared results are counted by compared result counters 203, 213 and 223 and based on these counted results, transmission timing counters 204, 214 and 224 successively output the respective data stored in the memories to the global bus.

Description

[Detailed description of the invention]

0001

[Industrial Field of Application] The present invention provides key data, etc. stored in the plurality of memories in a multiprocessor configuration in which a plurality of processor elements and a plurality of memories respectively connected to each processor element are connected by a global bus. The present invention relates to a parallel sorting device that sorts data in a desired order and outputs it via a global bus.

0002

2. Description of the Related Art In a system in which data is distributed and stored in a plurality of modules, it is necessary to sort the keys of the stored data in ascending order (descending order) and output the same to the outside.

[0003] Several algorithms for sorting processing have been proposed, one of which is the parallel counting sorting method [
Yasuura, Takagi: "High-speed sorting circuit using parallel counting sort", Transactions of the Institute of IEICE, 82/2, Vol. J65-D
, No. 2, pp. 179-186 (1982)]. The counting sorting method, which is the basis of parallel counting sorting, consists of two processes: ranking processing and rearranging processing.

[0004] Ranking process: The ranking of each key data (a part of record data) is determined.

[0005] Sorting process: Record data is sorted based on the results of the ranking process.

[0006] To explain the ranking process, the modules that make up the system count how many pieces of key data smaller (larger) than the key data it owns are in other modules, and based on the counted number. to determine the ranking. On the other hand, regarding sorting processing, there is a method in which key data is sent according to arbitrary rules (for example, the order of addresses assigned to each module), and the sent data is sorted based on the ranked key data. I'm picking it up. Parallel count sorting is a method of executing the above ranking process in parallel for each module.

The processing order of the conventional parallel counting sort will be explained using FIG. Parallel counting is performed under a multiprocessor configuration in which processor elements 100, 110, 120 connected to memories 101, 111, 121 and a control processor 130 that performs interface control with an external information processing device (host) are connected via a global bus 150. Assume that sorting is performed. Processor elements 100, 110, 12
In the memories 101, 111, and 121 connected to 0, two items, a key (key data) and a record (record data), are stored as a pair for each address.
Address 1 of the memory 101 of the processor element 100 has the key 456, record B; address 1 of the memory 111 of the processor element 110 has the key 123, record A; address 1 of the memory 121 of the processor element 120 has the key 456, record C. , and the control processor 130 includes each processor element 100, 110, 12.
Buffer 14 for receiving data transmitted from 0
Assume that it has 0.

When an ascending sort instruction request is sent from an external information processing device (host) to all processor elements 100, 110, 120 via control processor 130 and global bus 150, each processor element 100, 110, 1
20 accesses the key data stored at address 1 in the memory 101, 111, 121, and holds the key data corresponding to the instruction in the register 102, 112, 122. The key data is stored in registers 102 and 11.
2,122, the processor elements 100, 110,
120 is the global bus 1 after the above processing is completed.
50 bus rights to the control processor 130, and after acquiring the bus rights, key data is transmitted to the other processor elements 100, 110, and 120. First, processor element 100 acquires bus rights and transmits key data 456 to global bus 150. Processor element 11
0 receives the key and compares it with the key 123 stored in the register 112. Since it is found that the key data in the register 112 is smaller than the key data transmitted from the processor element 100, the counter 113
However, since the key data 789 in the register 122 of the processor element 120 is larger than the key 456, the counter 123 is counted by +1. It is not counted by the transmitting processor element 100.

[0009] When the above-mentioned transmission of key data between processor elements is performed for all processor elements 100, 110, 120, the counters 103, 113,
The value of 123 is updated to 1, 0, 2. This counter 1
The values 03, 113, and 123 are ranks assigned based on the key data. When the ranking process is completed, the processor elements 100, 110, and 120 transfer the record data including the key data to the global bus 15 in the order of the processor elements 100, 110, and 120 by the bus arbitration of the control processor 130 as before.
0, and control processor 130 sequentially stores those data in buffer 140. However, the order in which the control processor 130 receives data (keys and records) transmitted from multiple processor elements in the buffer 140 does not necessarily correspond to the sorted order in which the data is transmitted to an external information processing device (host). does not match. FIG. 3 shows the state after the processor element 100 has sent the data.

[0010] In order to avoid such problems, it is possible to add a function to the control processor to rearrange data, or to have the control processor poll the processor elements.

[0011]

The above-mentioned method has problems in that the buffer capacity increases, making it uneconomical, and the execution time increases due to polling.

The present invention has been made in view of the above, and
The purpose is to provide a parallel sorting device that is economical and can perform sorting in a relatively short processing time.

[0013]

[Means for Solving the Problem] In order to achieve the above object, a parallel sorting device of the present invention stores data stored in a plurality of memories respectively connected to a plurality of processor elements commonly connected to a global bus. a parallel sorting device for sorting data in a desired order and outputting the data via a global bus, comprising: sending means for sending data stored in each memory to the global bus in turn from each memory; and each processor element. a comparing means for receiving each data sent out to the global bus by the sending means and comparing the received data with data stored in each memory; and a counter for counting the comparison results by the comparing means. and a transmission timing counter for controlling each data stored in the memory to be sequentially output to a global bus based on the counting result of the counting means.

[0014]

[Operation] In the parallel sorting device of the present invention, the data stored in each memory is sent to the global bus in order, each received data is received by each processor element,
This received data is compared with the data stored in each memory, the comparison result is counted, and each data stored in the memory is sequentially output to the global bus based on the counted result.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the drawings.

FIG. 1 is an overall configuration diagram of a parallel sorting device according to an embodiment of the present invention. In the figure, a plurality of processor elements 200, 210, and 220 are connected in common and in parallel to a global bus 250, and are also connected to a control processor 230 via the global bus 250. This control processor 230 is further connected to an external information processing device (host).

Each processor element 200 (210, 220
) are respectively internal memory 20 as shown in detail in FIG.
1 (211, 221), a register 202 (212, 222) for registering data read from the internal memory, and a magnitude comparison circuit 205 (215) for comparing the magnitude of the key data sent from the register and the global bus 250.
, 225), +1 based on the comparison result of the magnitude comparison circuit.
Comparison result counter 203 (213, 2
23), a transmission timing counter 204 (214, 224) that performs a countdown according to the number of data transmitted on the global bus 250, and when the content of the comparison result counter reaches 0, instructs the register to transmit. It is composed of a transmitting circuit 206 (216, 226).

The external information processing device (host) transmits an ascending order sort instruction request to the control processor 230 of the parallel processor, and the control processor 230 receives the instruction and sends the command to all processor elements 200 via the global bus 250. , 210, 220. Processor element 2
00, 210, 220 receive the relevant command from the control processor 230, the internal memories 201, 211, 221
A read access is made to the key data at address 1 of the instruction, and if key data corresponding to the instruction is held, it is stored in the registers 202, 212, and 222. This process is carried out by each processor element 200, 210, 220.
are processed simultaneously. That is, the key data 123 is stored in the register 202, and the key data 789 is stored in the register 212.
, key data 456 is stored in the register 222.

Next, all processor elements 200, 210,
220 transmits key data to other processor elements 200, 210, 220 via the global bus 250, and each processor element 200, 210, 220 transmits a pre-allocated processor address to the timing counter 204, 214, 224, and the transmission timing counters 204, 214, 224 are subtracted by the number of data transmitted on the global bus 250, and when the counter value becomes 0, the registers 202,
212 and 222 transmit data [here, it is assumed that the data is transmitted in the order of processor element 200, processor element 210, and processor element 220]. The other processor elements 210 and 220 transfer the key data 123 sent from the source processor element 200 to the global bus 25.
0, and the magnitude comparison circuits 215 and 225 compare the magnitude with the contents of the registers 212 and 222. If the registers 212, 222 are larger than the key data received from the global bus 250, the contents of the comparison result counters 213, 223 are updated by +1. As a result of this processing, the comparison result counter 21 of the processor element 210
The value of 3 is updated to 1, and the value of the comparison result counter 223 of the processor element 220 is also updated to 1. Next is processor element 2
10 becomes the transmission source and performs similar processing. The processor element 220 also executes the above processing.

Next, each processor element 200, 210,
220 transmits the final value of comparison result counters 203, 213, 223 to timing counters 204, 214, 224.
At the same time, the key data and record data are set in the registers 202, 212, and 222. FIG. 1 shows the results of the processing up to this point for the entire system. Next, the transmission timing counters 204, 214, 2
24 counts down according to the number of data on the global bus 250, and when the transmission timing counters 204, 214, 224 reach 0, the transmission circuits 206, 216, 226 transmit the data stored in the registers 202, 212, 222. An instruction is issued to send to the global bus 250. Transmission timing counters 204, 214, 22
Processor elements where 4 is not 0 continue to count down the number of data by the transmission timing counters 204, 214, 224, and the transmission timing counters 204, 214,
Registers 202, 212, 222 until 224 becomes 0
The data stored in is not transmitted.

Specifically, when data transmission is started from the state shown in FIG.
Key 123 and record A stored in register 202
The control processor 23 via the global bus 250
Thereafter, data is transmitted to the processor element 220 and then to the processor element 210 in this order.

The control processor 230 sequentially receives data (key data, record data) transmitted from each processor element 200, 220, 210 through the global bus 250 in the course of the above processing.
It becomes possible to obtain sorted data in stream format.

[0023]

[Effects of the Invention] As explained above, according to the present invention,
The data stored in each memory is sent to the global bus in order, each received data is received by each processor element, this received data is compared with the data stored in each memory, and the comparison result is Since each data stored in memory is sequentially output to the global bus based on the counting results, buffers and processing time for sorting are no longer required, making it economical and faster. This makes it possible to transmit sorted data in stream format.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of a multiprocessor system having a parallel sorting device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the internal configuration of a processor element used in the parallel sorting device of FIG. 1;

FIG. 3 is an overall configuration diagram of a conventional multiprocessor system that executes conventional parallel counting sort.

[Explanation of symbols]

200, 210, 220 processor elements 201, 2
11, 221 Internal memory 202, 212, 222
Registers 203, 213, 223 Comparison result counter 204,
214, 224 Transmission timing counter 205, 2
15, 225 Size comparison circuit 206, 216, 226
transmitting circuit

Claims (1)

[Claims] 1. A parallel sorting device that sorts data stored in a plurality of memories each connected to a plurality of processor elements commonly connected to a global bus in a desired order and outputs the data via a global bus. a sending means for sequentially sending the data stored in each memory to the global bus from each memory, and a sending means provided in each processor element to receive each data sent to the global bus by the sending means. and a comparing means for comparing the received data with data stored in each memory, a counting means for counting the comparison result by the comparing means, and a data stored in the memory based on the counting result of the counting means. 1. A parallel sorting device comprising a transmission timing counter that controls each data to be sequentially output to a global bus.