JPS5981734A - Data ranking device - Google Patents

Abstract

PURPOSE:To form simply the ranking of data by rearranging the data sent from upper places in a sortable code system and the stored data in a fixed procedure after comparing the quantities of both data. CONSTITUTION:The n-th data is sent to a CPU7 from a higher rank computer 1 through an input register 3 and an I/O control circuit 5 and compared 10 with the data stored in an RAM9. If the n-th data is smaller than the minimum existing data, the n-th data is put into an address O. Then the addresses of the existing data are moved up one by one. While the n-th data is fed to the (n-1)-th address if the data is larger than the maximum existing data. If the n-th data has a quantity between the maximum and minimum existing data, the existing data is divided into two parts. These divided data are compared with the maximum and minimum data of each region to decide their regions respectively. Then the above-mentioned operation is carried out to these regions. This operation is repeated to make it possible to form the ranking of data just with the hardware such as an input/output means, a comparing means, etc. in a simple way at a low cost.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data sequencing device using a microcomputer or the like.

Generally, if you try to process a large number of tasks simultaneously on one medium-sized or large-sized computer, even a high-performance computer may not be able to handle all the tasks. For this reason, individual tasks have been transferred to microcomputers and distributed as firmware, improving handling convenience and data throughput. ,by the way,
Up until now, most of the data ordering has been done using software, and there has never been a type of hardware such as a microcomputer that can do it cheaply and easily.

An object of the present invention is to enable data ordering to be performed easily and inexpensively using a type of hardware such as a microcomputer.

For this purpose, the present invention uses a type of hardware such as a microcomputer to arrange data having a classifiable code system, which is randomly input from a host computer, in a certain order.

Hereinafter, the present invention will be explained in detail based on an embodiment shown in the drawings.

The figure is a circuit diagram of this embodiment. In this figure, (1
) is a host computer, and (2) is a firmware-based data ordering device of this embodiment. This data ordering device (2) includes an input register (3), an output register (4).
), input/output control circuit (5), ROM (read-only memory) (6), CPU (central processing unit) (7), control circuit (8), RAM (random access memory) (
9) , comparison circuit C1l, first address counter aυ
, address calculation circuit (2), - second address counter (
), odd number/4Fm number circuit α→, AND circuit αυ,
Start signal generation circuit H.

and a ready/busy signal (interrupt signal) generating circuit α. The input register (3) sends data from the host computer (1) to the CPU (y). The output register (4) sends data from the CPU (7) to the host computer (1). The input/output control circuit (5) controls the output of the data. The ROM (6) stores a program for processing data input from the host computer (1). The CPU (7) performs overall control. A control circuit (8) controls the operation of each circuit (9) to 0'3 based on signals from the CPU (7). Comparison circuit (
When IG wants to arrange data having a code system that can be classified in a certain order (for example, in ascending order) in the order of each address number in RAM (9), the IG sorts the data input from CPU (7) and the RAM ( 9) Compare the data already stored in memory according to their order. 1st. 2nd address counter 0ηα [present], address calculation circuit (
Functions such as 6) will be clarified in the following operation explanation.

Next, the operation will be explained. For the convenience of this explanation, it is assumed that the data is a data series (for example, a combination of numbers) that has a code system that can be classified and does not have the same number. Also, consider, for example, the order of small numbers as a fixed order.

First, the start command signal is sent to the host computer (1
) is input to the start signal generation circuit OQ.

The start signal generation circuit aQ inputs a start signal to the CPU (7) via the input/output control circuit (5). The data ordering operation thus begins. At this starting point, R.A.
The memory contents of M(9) have been cleared. In this state, the first data is input from the host computer (1) to the input register (3) through the data bus, and at the same time, the first data is input from the CPU (7) to the address of address number "0" in the RAM (9). and stored in memory. At this time, the control circuit (8) simultaneously sets the count value of the first address counter (1υ) to rOJ.
When the th data is inputted from the CPU (7) to the RAM (9), the comparing circuit diagram compares the magnitude between the first data and the second data at the address number rOJ. As a result of the comparison output indicating that the second data is smaller, the first data is moved to the address with address number "1", and the second data is entered into the address with address number "0". On the other hand, due to the way the comparison shows that the first data is smaller, the first data will remain as it is,
The second data enters the address with address number "1". At this time, the count value of the first address counter aη becomes "1". Next, the 8th data is RAM (9)
, the comparator circuit QQ first compares the first and eighth data in magnitude, and then compares the second and third data in magnitude.

If the 8th data is smaller than the 1st data, each address of address number rOJ Ill r2J has the 3rd, 1st, and 2nd data (assuming that the 1st data is smaller than the 2nd data). are input in this order, and if the 8th data is larger than the 2nd data, the 1st, 2nd, and 8th data are input in this order to each address of address number rOJ rlJ r2J. be done.

At this time, the count value of the first address counter 0υ becomes "8" at the same time. In this way, the data are successively compared in magnitude. Then, the nth data is stored in RAM (9
), the nth data is compared with the data stored in the address with the lowest address number rOJ, and the nth data is compared with the data stored in the address with the lowest address number rOJ. A comparison is made with the data stored at address 2J. If the former,
The n-th data is placed in the address with the lowest address number "0" and other data is transferred to an address with one address number higher. If it is the latter, put the nth data into the address of address number [n-IJ.

At the same time, the count value of the first address counter αυ becomes In-IJ. However, when there is a comparison output indicating that it is neither of these two, the address calculation circuit @ calculates the address number rOJ~rn-IJ(7) 7
The address area is divided into two by performing the trass calculation.
(However, it goes without saying that when the number of addresses belonging to each area is both even numbers, a combination of even numbers and odd numbers or both odd numbers is also possible.) Half the area is set as the second address counter α. Then, after checking which area the nth data is in, if it is in one area, the nth data is memorized at the address with the lowest address number and the highest address number in this area. Compare the size and rearrange the data in the same way as above. When this area is reached, but there is a comparison output indicating that it is neither the former nor the latter as described above, this area is further divided into two and the same process is repeated. In this way, it is finally determined which address number the nth data should go into. In this way, the order of data from 1st to nth is determined. At the same time, the count value of the first address counter 0) becomes "n-IJ."

It should be noted that when the area is divided into two, the number of addresses that cannot be deleted any further becomes an odd number of "1". At this time (2 is an odd/even circuit α, a logic "1" signal is input to the AND circuit 0!9. As a result, the AND circuit α outputs a logic "1" signal to the control circuit (8). By doing so, the ranking position of the data is uniquely determined.

When all the data have been sequenced, the CPU (7) passes through the input/output control circuit (5) to the ready/busy signal generation circuit α.
A signal to that effect is input to the power source.

The ready/busy signal generating circuit aη notifies the end of the data sequence by sending a ready signal to the host computer (1).

As described above, according to the present invention, the function of arranging data having a code system that can be classified randomly inputted from a host computer in a certain order is a type of input means, comparison means, etc. This can be done easily and inexpensively using lightweight hardware.

[Brief explanation of the drawing]

The figure is a circuit diagram of an embodiment of the present invention. (1)...Upper computer, (2)...Data sequence device, (7)...CPU, (9)...RAM,
<it)... Comparison circuit, 0]) αt... 1st ° 2nd
Address counter, @... address calculation circuit, 04)
...Odd/even circuit applicant: Takasugi Seisakusho Co., Ltd. Agent: Patent attorney: Kazuhide Okada

Claims (1)

[Claims] (1) A means for inputting data having a classifyable code system randomly inputted from a host computer into a memory, and a means for inputting first data inputted into the memory into each address of the memory in a certain order. Among the input data, the second . means for comparing the order with the eighth data, and a comparison output indicating that the first data should be input to an address having an address number lower than the second data or higher than the eighth data; Data is input to the address having the lowest or highest address number, and by comparing and outputting neither, the addresses having address numbers from the lowest to the highest are divided into at least two areas, and the first data is divided into at least two areas. and means for repeating the comparison after checking if the area falls within the range of .