JPH01309549A - Digital signal reproducing device - Google Patents

Abstract

PURPOSE:To improve recording density and to reduce a decoding error rate by providing a specific product sum means, a subtraction means and a decoding means decoding a digital signal based on the output of the subtraction means. CONSTITUTION:The title device is provided with a product sum means 2 which calculates products mi=Ci.yk-1 (i=1...Q) between Q sets of consecutive reception signal series yk-1 (i=1...Q) from a time (k-Q)T till a time (k-1)T and prediction coefficients Ci (i=1...Q) with respect to Q set of consecutive noise and calculating the sum (s) of the Q sets of products (T is a sample time interval of the reception signal), a subtraction means 1 subtracting the output of the product sum means 2 from the reception signal yk at a time kT and a signal means decoding the digital signal based on the output of the subtraction means 1. Thus, the noise prediction coefficient is multiplied with the past equalizing signal and the result is added to eliminate noise correlation and to minimize the noise. Thus, the decoding error rate is reduced and the recording density is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital signal reproducing device that effectively decodes signals digitally recorded or transmitted at a high rate with fewer errors.

Conventional technologyWhen recording and reproducing digital signals at high density,
Due to the high frequency component attenuation characteristics of the reproduction system, the high frequency components of the recorded/reproduced digital signal are attenuated, resulting in waveform interference with adjacent data. This waveform interference particularly lowers the peak level of the reproduced signal, resulting in substantial deterioration of the signal-to-noise (S/N) ratio. This causes a deterioration of the decoding error rate and is a major factor hindering the improvement of recording density. Conventionally, when such waveform interference is a problem, it is necessary to correct the high frequency component attenuation characteristics of the recording/reproducing system. A waveform equalization circuit having a characteristic opposite to this attenuation characteristic, that is, a high frequency emphasis characteristic, is inserted to eliminate waveform interference regarding the reproduced signal. If the noise level is sufficiently small or the degree of high-frequency emphasis of the equalization circuit is small, waveform equalization has almost no adverse effects and almost ideal error rate characteristics can be obtained.

In addition, the higher the recording density (the higher the recording rate), the narrower the frequency band of the recording/reproducing system relative to the recording rate, and the greater the amount of waveform interference. In this case, waveform equalization is unavoidable.
Moreover, since the degree of high-frequency emphasis of the equalization circuit becomes very high, the amount of equalization noise at the output of the equalization circuit also becomes large. In digital VTRs, etc., which require ultra-high density recording, the data rate is extremely high, and the amount of noise before equalization is also not small. Make it.

On the other hand, it is known that for uncorrelated noise, the Viterbi decoding method provides better error rate characteristics than the normal bit-by-bit decoding method. However, due to the correlation of the equalization noise at the output of the equalizer, the optimum performance of this Viterbi decoder is not achieved and its advantage over conventional bit-by-bit decoding methods is negligible.

Problems to be Solved by the Invention As described above, conventional digital signal reproduction techniques not only increase the amount of noise, but also render the use of potentially superior decoding methods meaningless. . This means that as the recording density increases, the decoding error rate deteriorates exponentially, which is a major obstacle in promoting high-density recording.

An object of the present invention is to improve recording secrecy by developing a digital signal reproduction technique based on the above-mentioned prior art, which is less susceptible to the adverse effects of noise increased by equalization noise and the correlation of equalization noise.

Means for Solving the Problem When the sample time interval of the received signal is T, time (k
−Q) Q consecutive reception signal sequences Y h−+ (1:I”Q) from T to time (k−1)T and prediction coefficients C+ (1=1 to subtraction means for subtracting the output of the product-sum means from each product m+: C+・yh−+(1=I to Q), this stage, and the received signal y at time kT, and the subtraction means A digital signal reproducing device comprising decoding means for restoring a digital signal based on the output of the digital signal reproducing device.

Operation The present invention removes noise correlation by multiplying a past equalized signal by a noise prediction coefficient and adding the multiplied signals. Furthermore, waveform interference occurs in the signal components during this process, but since this interference is completely cause and effect, for example, by using the Viterbi decoding method, signal components including this interference can be accurately decoded.

In other words, even if waveform equalization is performed, optimal error rate characteristics can be achieved.

EMBODIMENTS In the following, an outline of the present invention will first be shown, and then an example of means for realizing the present invention will be explained using a block diagram.

Let T be the sample time interval, and let the sample at time kT be expressed as a subscript. If the recorded bit string is (bk) then, for example, digital VT
In the case of R, since the reproduction system has differential characteristics, the reproduction signal component Xk at the equalization circuit output is expressed by equation (1).

xk=bk bb-+' (1)
Also, the equalization noise, which is the noise at the equalizer output, is n.

Then, the equalization circuit output zk is given by equation (2).

Zk=Xk0nk (2) By the way, the fact that noise has a correlation means that future noise can be predicted to some extent from past noise by using this correlation. The residual noise that remains after removing this predicted noise from the true noise becomes uncorrelated so-called random noise. Here, the prediction coefficient is c + (+=1”Q)
Then, the prediction noise r1 is given by the following equation (3).

Here, the noise autocorrelation coefficient R1 is expressed by the following equation. However, E[·] represents the average value.

R+=E [nk@nk-+1 (4
) In order for Equation (4) to give the correct prediction noise, the prediction noise r1k and the true noise nk-1 (j=1+2+...'+
The correlation coefficients of
+−+=R+−+ ([i
) A prediction coefficient of 01 is obtained from equations (4) to (6), making it possible to predict noise that satisfies statistical properties. At this time, the residual noise n remaining after subtracting the predicted noise fib from the true noise nb becomes uncorrelated so-called random noise.

Here, if Zb-+ is substituted for n to 1 in equation (3), the result 2 is given by equation (7).

Equation (7) is expressed as the sum of a linear combination of predicted noise and an ideal reproduced signal. Therefore, from the equalization circuit output zk, equation (7)
The decoder input signal yk obtained by subtracting yk is expressed by equation (8).

Next, a Viterbi decoding method for restoring a digital signal based on equation (8) will be described. However, Q in equation (8)
=1, that is, previous value prediction is taken as an example. In this case, equation (8)
can be rewritten as equation (8).

Vb=Xb'+nb (
9) However, Xk"=bk-(1+01)・b+-+10+-bk-
2 (10).

Here, as shown in Fig. 2, four states S + (1"0~
3), the input/output correspondence becomes as shown in FIG. Further, FIG. 4 shows a state transition diagram. In FIG. 4, the symbol attached to the arrow represents bh/yb. here,
A data series of length [b+,
The path on the state transition diagram corresponding to ba, ..., bL [
5(0) ibl, b2. ..., bL is given, the decoder input sequence [Yl, y2 . ..., yL] is given by the following equation, assuming that the noise sample values for each bit cell are mutually independent.

-In 1) [y++Y2+...'+YL I 5
(0);b++b2+"・+bL here, 5(k-1
) represents the state at time t=(k-1)T.

From equation (11), it can be seen that the negative log-likelihood function of a given path is expressed as the sum of the negative log-likelihood functions of the individual branches that make up the path. Therefore, if the length of a branch is represented by a negative log-likelihood function, the path with the minimum length can be selected and the corresponding data sequence, that is, the maximum likelihood sequence, can be decoded using the following method.

The minimum value of the path length leading to each state at a certain time is called a metric, but for the present invention, the metric for the state S + (+=θ~3) at t=kT is defined as m
When expressed as k(Sl), the relationship shown in equation (12) is obtained from FIG.

Here, the noise sample value nk has a mean value of zero and a variance σ2
Assuming Gaussian noise of
k is a Gaussian variable with mean value Xk' and variance σ2. Therefore, for example, from state S (k-1) = S e to bk =
1 enters, state 5(k) = S +
In the case of transition to yk = 1 from Fig. 4, +(1/2 V k)/σ'
(13). Similarly, the expression (
Other negative log-likelihood functions in (12) can also be calculated, and the first term on the right-hand side of equation (I3) is present as a common term in all of them. Therefore, by removing this common term and further dividing by 1/σ2, generality is not lost even if normalization is performed. In this way, normalized metrics as shown in the following equations (I4) to (17) are obtained.

mk(SQ)=mln(mk-+(Sa)+1k291
mv-+(S2)+1k291 (14)mb(Si
)=mjn(mk-+ (S9)+lk", mv-+
(S2)+1k21) (15)mb(S2)=mj
n(mb-+(Si)+To12+mk-+(Sa)+
1k32) (te)mb(S3)=mln(mb-
+(Si)+1k291mb-+(S3)+1%3)
(17) Here, 1% I is state S (k-1) = S
l (○～3) to state S (k) = S + (
represents the normalized length of the branch that transitions from j = 0 to 5),
It is given by the following equation.

However, if we choose Sa as the initial state, then mb(
Sll)=ol mk(SI)=ω+(f≠0)
(19).

At time t=kT, among the paths leading to state 5J (j20~3), have the metrics given by equations (I4) to (I7) mk(Si)(j''o~3) Only the path is left as the path that has the possibility of becoming the maximum likelihood path,
Others are thrown away. This path is called a surviving path, and the probability that the surviving paths at time kT are unified at time (k-1)T increases with l. The Viterbi decoder of the present invention decodes this converted path as the maximum likelihood path.

Theoretically, the metrics can be calculated using equations (I4) to (17), but in practice, the following overflow prevention measures are required to prevent metrics from overflowing. As can be seen from equations (I4) to (17), the absolute size of the metrics is not important, but only the relative magnitude relationship between the metrics.

In other words, correct decoding is possible if the mutual precedence difference between metrics can be maintained. This is N mb-+(Se
) relative to zero, m++-+(Su)I=
1 to 3), the magnitude relationship of the likelihoods is maintained accurately. Therefore,... Equations (14) to (1
After completing the calculation in 7), subtract mk(So) from mb(Si)(i:O~3) and create a new m h(Si)(1
:0 to 3), it is possible to prevent the above metric from overflowing. Newly obtained mb(Sll
) is zero, so it can be omitted for metric calculation.

Next, a means for realizing the present invention will be explained.

FIG. 1 shows a block diagram of this embodiment. In FIG. 1, a subtracter 1 subtracts a signal 2k from a product-sum circuit 2 from an equalized signal Zk from an equalization circuit O.

The product-sum circuit 2 calculates the product of the previous equalized signal Z k-+ and the prediction coefficient C5. Note that when the number of prediction stages Q is 2 or more, the product-sum circuit 2 performs the intermediate class calculation of equation (7). As a result, y given by equation (8) appears at the output of subtracter 1.

The arithmetic circuits 3 to 8 have the normalized branch lengths 1-1.1 kIQ, 1k13.1, 2a11. +!
Calculate l and l-2 respectively. After this, the adder 9 calculates the eclipse of the m1n-13==12- function in equation (14), the adder 10 calculates the eclipse of the min function in equation (I5), and the adder 11 calculates the eclipse of the m1n-13==12- function in equation (16). The adder 12 calculates the eclipse of the min function of formula (I6), and the adder 13 calculates the flower of the min function of formula (I7).

The comparison and selection circuit 14 realizes equation (I4), the comparison and selection circuit 15 realizes equation (15), and the comparison and selection circuit 16 realizes equation (1).
6), and the comparison and selection circuit 17 realizes equation (17). It should be noted that each of the comparison and selection circuits 14 to 17 also outputs 0 if flowers are selected, and 1 if eclipses are selected. The subtraction circuit 18 subtracts the output of the comparison and selection circuit 14 from the output of the comparison and selection circuit 15, the subtraction circuit 19 subtracts the output of the comparison and selection circuit 14 from the output of the comparison and selection circuit 16, and the subtraction circuit 20 subtracts the output of the comparison and selection circuit 17. Comparison selection circuit 14
Subtract the output of

Shift register 21 is in state SL! The bit string corresponding to the surviving path leading to state S1, shift register 22, is the bit string corresponding to the surviving path leading to state S1, shift register 2.
3 is a bit string corresponding to the surviving path leading to state S2,
The shift register 24 holds bit strings corresponding to the surviving paths leading to state S3.

The switch 25 is based on the output of the comparison selection circuit formula 14.
When the flower of the min function is selected in equation (I4), the contents of the shift register 21 are held as they are, and the min function is selected.
If the eclipse of the n function is selected, the shift register 21
Copy the contents of shift register 23 to . After this, in either case, the contents of the shift register 21 are shifted to the right by one bit, and a binary value of 0 corresponding to the state SlI is fed.

The switch 26 is based on the output of the comparison selection circuit formula 15,
When the flower of the min function is selected in equation (I5), the contents of the shift register 21 are copied to the shift register 22.1. , min function is selected, the contents of the shift register 24 are copied to the shift register 22. After this, in either case, the contents of the shift register 22 are shifted to the right by one bit, and a binary value 1 corresponding to the state S is fed.

The switch 27 is based on the output of the comparison selection circuit formula 16.
In equation (16), if the flower of the min function is selected, the contents of the shift register 22 are copied to the shift register 23, and if the eclipse of the min function is selected, the contents of the shift register 24 are copied to the shift register 23. Copy the contents. After this, in either case, the contents of the shift register 23 are shifted to the right by 1 bit, and the binary value O corresponding to state S2 is
feed.

The switch 28 is based on the output of the comparison selection circuit formula 17.
In equation (I7), if the flower of the min function is selected, the contents of the shift register 22 are copied to the shift register 24, and if the eclipse of the min function is selected, the contents of the shift register 24 are retained as they are. do. After this, in either case, the contents of the shift register 24 are shifted to the right by one bit, and a binary value of 1 corresponding to state S3 is fed. In addition, each shift register is provided with a buffer,
This buffer always holds the updated contents of the shift register. Furthermore, when copying from shift register A to shift register B, it is assumed that the contents of the buffer of shift register A are copied to shift register B. This allows smooth copying between shift registers.

As a result of the above, if the length of each shift register is long enough,
Near the final stage of the shift register, the surviving lotuses are unified, and the same result can be obtained no matter which shift register the output is taken from. However, if the length of the shift register is not sufficient, the value may differ depending on the output shift register. In such cases, it makes the most sense to choose the output from the surviving path with the smallest metric. That is, equations (14) to (17
), the minimum value is obtained, that is, the most probable surviving path is found, and the output is taken out from the shift register holding this surviving path. For example, the minimum value of the metric is mk(So)
In this case, the output can be taken out from the shift register 21 that holds the surviving path leading to state S9. In addition,
To reduce calculation time, the minimum metric is subtraction circuit 1
It is better to do this for 8 to 20 inputs. Although these circuits are not shown in FIG. 1, they can be easily constructed.

As described above, it is possible to easily realize a digital signal reproducing apparatus that can largely eliminate the influence of high-frequency noise on the isophoric lid output and can obtain a maximum likelihood decoding sequence that can minimize errors.

Effects of the Invention The present invention can effectively remove noise correlation and minimize the amount of noise. As a result, the decoding error rate can be ideally reduced and this excellent performance can be achieved with a realistic compact circuit scale. Therefore, it can be widely applied not only to professional use but also to consumer digital VTRs, optical discs, digital audio equipment, high-speed digital transmission equipment, etc.
Enables highly reliable reproduction of digital signals. As described above, the scope of application of the present invention is wide, and its practical effects are significant.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a digital signal remastering device according to an embodiment of the present invention, FIG. 2 is a state definition diagram, FIG. 3 is an input/output correspondence diagram, and FIG. 4 is a state transition diagram. 0... Equalization circuit, 1. 18, 20... subtraction circuit,
2.φ.product-sum circuit, 3-8...operation circuit, 9-13.
・φ adder circuit, 14 to 1711 ・Comparison selection circuit, 2
1-24...shi, photoresist & buffer, 25-2
8...Switch.

Claims (2)

[Claims] (1) When the sample time interval of the received signal is T, Q consecutive received signal sequences y_k_-_1 (i=1 to Q) from time (k-Q)T to time (k-1)T and Q
Prediction coefficients c_i (i=1~Q
) of each product m_i=c_i・y_k_−_i(i
=1~Q) and the sum of these Q products▲Mathematical formula, chemical formula,
▼, subtraction means for subtracting the output of the product-sum means from the received signal y_k at time kT, and decoding means for restoring a digital signal based on the output of the subtraction means. A digital signal reproducing device characterized by: (2) The decoding means compares the output of the likelihood calculating means with a likelihood calculating means for calculating a new likelihood from the current output of the subtracting means and the likelihood for the previous output series of the subtracting means. , a plurality of comparison and selection means that output only either the smaller one or the larger one, and the output of one of the plurality of comparison and selection means is subtracted from the output of the other comparison and selection means, and the result is 2. The digital signal reproducing apparatus according to claim 1, further comprising subtracting means for determining the likelihood for the output sequence of the previous product-sum means.