JP2005223405A - Maximum likelihood decoding method and maximum likelihood decoding apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize adaptive adjustment of the reference level of Viterbi decoding without increasing the circuit scale. <P>SOLUTION: Two different levels v0(t) and v1(t) are stored to each of state transitions t in Viterbi decoding. A metric m(t) with respect to the state transition t is defined as m(t)=v0(t)×(2×s(n)-V1(t)) when a signal s(n) äwherein n is time} is received. The v0(t) is the reference level given by a simple integer ratio with respect to different t values, and the V1(t) is the reference level with higher accuracy than that of the v0(t) and can fluctuate in the vicinity of the v0(t). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a maximum likelihood decoding method and a maximum likelihood decoding device for decoding a reproduction signal from a recording medium and a reproduction signal acquired by a transmission medium into original information, and particularly a maximum likelihood decoding method applying partial response maximum likelihood decoding and The present invention relates to a maximum likelihood decoding apparatus.

  In general, a playback-side device used in data recording / playback technology using various recording media is a pickup device that reads a signal recorded on the recording medium as a playback signal, or an original from a playback signal read by this pickup device. It has a decoding device for decoding binary data.

Further, in such a recording / reproducing technique, with the recent increase in recording density, as a more reliable decoding apparatus, a reproduction signal is generated based on a decoding method called a so-called partial response maximum likelihood decoding (PRML). Those configured to decode binary data are known.
The partial response maximum likelihood decoding method is a partial response technique for reproducing a data string through a channel having a predetermined impulse response, and a data string estimated as the original data string from all the data strings is decoded. This is a decoding technique that combines the maximum likelihood decoding technique.

In this partial response maximum likelihood decoding method, a state composed of a small number of consecutive bits is defined, and a transition pattern between two states and a Viterbi level that is a signal level corresponding to the transition are known information. It is prepared as.
The purpose of this decoding method is to search for a bit sequence that maximizes the posterior probability obtained from the reproduced signal. For this purpose, first, the signal level of the detected reproduction signal is compared with the Viterbi level, and the conditional probability for each state transition is calculated.

For example, there are two states, 0 and 1. At this time, there are four state transitions: 0 → 0, 0 → 1, 1 → 0, 1 → 1. Further, it is assumed that Viterbi levels −1, 0, 0, 1 are output corresponding to state transitions 00, 01, 10, 11 (corresponding to PR (11)). Here, if there is no noise, the signal level of the reproduction signal becomes one of -1, 0, 0, 1 while following the state transition in the bit sequence of the original recording information.
On the other hand, when there is noise, the signal level of the reproduction signal at each time is output as a level having a distribution centering on one of the above values according to the state transition. Here, let r (n) be the level of a signal obtained when there is noise (n represents the sampling time). Usually, the noise distribution is considered to be a general Gaussian distribution. When the posterior probability of state transition is obtained under the above conditions, from the calculation of conditional probability,
p00 = A · c00 · exp ( - ((r (n) +1) / σ00) 2/2)
p01 = A · c01 · exp ( - ((r (n) -0) / σ01) 2/2)
p10 = A · c10 · exp ( - ((r (n) -0) / σ10) 2/2)
p11 = A · c11 · exp ( - ((r (n) -1) / σ11) 2/2)
become that way.
However, pxx is a posterior probability of state transition xx. A is a normalization constant and the sum of probabilities is 1.

On the other hand, c00,..., C11 are state transition prior probabilities (corresponding to the frequency of transition patterns). This value is conventionally assumed to be an equal probability. .Sigma.00,..., .Sigma.11 are the above-described noise standard deviations at the reference level corresponding to the state transition. Similarly to c, this value has been treated as the same value in the past.
The posterior probability of the bit sequence including the transition 00 or 01, 10, 11 is the product of the posterior probability of each transition and the posterior probability of the bit sequence up to 00, 01, 10, 11, or 11. It is represented by
Therefore, the posterior probabilities of the bit sequences up to 00, 01, 10, and 11 are q00, q01, q10, and q11, respectively, and the posterior probabilities of the bit sequences including 00, 01, 10, and 11 are q It is assumed that '00, q'01, q'10, and q'11. At this time,
LOG (q'00) = LOG (q00) + LOG (A)
+ LOG (c00) - (( r (n) +1) / σ00) 2/2
LOG (q'01) = LOG (q01) + LOG (A)
+ LOG (c01) - (( r (n) +0) / σ01) 2/2
LOG (q′10) = LOG (q10) + LOG (A)
+ LOG (c10) - (( r (n) +0) / σ10) 2/2
LOG (q′11) = LOG (q11) + LOG (A)
+ LOG (c11) - (( r (n) -1) / σ11) 2/2
The relationship holds.

  Here, the purpose of the partial response maximum likelihood decoding method is to search and select a bit sequence having the maximum posterior probability. However, since the actual search is performed by hardware composed of logic circuits, it is desirable that the number of complicated calculations such as exponential functions and multiplications be as small as possible. Therefore, paying attention to the relational expression obtained earlier, it can be seen that the exponential function is eliminated by using the logarithm of the probability instead of the probability. Furthermore, since the magnitude relationship is preserved between the probability and the logarithm of probability, the bit sequence that maximizes the posterior probability can have the maximum logarithm of probability.

From the above, the calculation of the posterior probability can be actually substituted with the logarithm of the probability.
Now, looking at the update of the logarithm of the posterior probability in detail, it can be seen that LOG (A) is common. Therefore, this term is omitted because it is irrelevant to the magnitude relationship. Since cxx is common, this term is also omitted. Finally, since σxx is also common, this portion is, for example, a half route.
As described above, after all, in the conventional partial response maximum likelihood decoding method, pm'00 = pm00− (r (n) +1) ²
pm′01 = pm01− (r (n) −0) ²
pm′10 = pm10− (r (n) −0) ²
pm′11 = pm11− (r (n) −1) ²
It can be seen that this can also be realized by sequentially selecting a bit sequence that maximizes.

Therefore, in partial response maximum likelihood decoding, the square of the difference between the detected signal and the reference level is defined as the metric, and the metric to which this metric has been sequentially added is defined as the path metric, and the path metric is minimized. The bit sequence is searched and decoded.
More generally, consider a case where the bit string of the state transition is t. Then, if the signal level of the detected signal is q (n) (time n) and the reference level for the state transition t is v (t), the metric m (t) of the state transition t is
m (t) = (q (n) −v (t)) ²
It is expressed. Then, the metrics obtained here are sequentially added corresponding to the state transition, and a bit sequence that makes the state transition that minimizes the obtained path metric is searched and decoded. As described above, in partial response maximum likelihood decoding, a metric is used instead of a probability, so that a complicated calculation such as an exponential function is not performed by a logic circuit.
However, looking at the metric m, the exponential function is gone, but the multiplier remains. Although this multiplication operation is not as complicated as an exponential function, it is more complicated than addition and subtraction, so it is desirable to reduce it as much as possible.

By the way, it is sufficient if the metric at the same time is known only in relative magnitude. Therefore, the metric can be redefined based on the metric m (k) for a certain state transition k. At this time, the newly defined metric m ′ (t) is
m ′ (t) = m (t) −m (k)
= (Q (n) -v (t)) ^2- (q (n) -v (k)) ²
= (V (t) -v (k)). (2.q (n)-(v (t) + v (k)))
It becomes.

Here, considering PQ (1221) and d = ± 1,
v (t = 0000) =-3
v (t = 0001) =-2
v (t = 1000) =-2
v (t = 1001) = − 1
v (t = 0011) = 0
v (t = 1100) = 0
v (t = 0110) = 1
v (t = 0111) = 2
v (t = 1110) = 2
v (t = 1111) = 3
It becomes.

Therefore, if k = 0011 is selected, since v (k) = 0, the metric is
m ′ (t = 0000) = − 3 (2q (n) +3)
m ′ (t = 0001) = − 2 (2q (n) +2)
m ′ (t = 1000) = − 2 (2q (n) +2)
m ′ (t = 1001) = − 1 (2q (n) +1)
m ′ (t = 0011) = 0
m ′ (t = 1100) = 0
m ′ (t = 0110) = 1 (2q (n) −1)
m ′ (t = 0111) = 2 (2q (n) −2)
m ′ (t = 1110) = 2 (2q (n) −2)
m ′ (t = 1111) = 3 (2q (n) −3)
It becomes.

Here, looking at the right side of m ′ (t), it can be seen that all are composed of simple multiplication coefficients and addition operations. Since the multiplication coefficient is a simple integer, it can be easily rewritten only by the addition operation. As a result, m ′ (t) can be created with a simple circuit that only has an addition operation.
That is, in the conventional Viterbi decoder that realizes partial response maximum likelihood decoding, the circuit scale is made as small as possible by changing the metric calculation method as described above.
However, in this case, in the conventional method, it is key that the reference level can be expressed by a simple integer ratio. Therefore, when the accuracy of the reference level is increased or adaptively changed so as to follow a subtle change in the reference level, it is not possible to use a method that performs only addition and subtraction as described above. For this reason, it is necessary to use a multiplier, and as a result, the circuit scale greatly increases.

  On the other hand, in an optical disc, the level corresponding to the reference level varies due to asymmetry, envelope variation, and frequency characteristic variation such as MTF, so it is necessary to adaptively change the reference level. Therefore, in order to realize these, it is necessary to consider a method capable of increasing the accuracy of the reference level and following subtle changes.

Therefore, in order to cope with such a situation, the reference level is adaptively changed without using a multiplier, and an equalization reference value used as a metric calculation reference is measured in advance and given in a table. A configuration has been proposed in which updating is performed sequentially based on the detection result of the Viterbi detector (see, for example, Patent Document 1).
In addition, as a configuration for easily performing metric calculation, a configuration in which path determination is performed by comparing the magnitudes of input signals has been proposed (see, for example, Patent Document 2).
Japanese Patent No. 3016366 Japanese Patent Laid-Open No. 7-46144

As described above, conventionally, a method of adaptively changing the reference level by simple arithmetic processing has been proposed, but a simpler and more appropriate method is required.
Therefore, the present invention memorizes two different reference levels for each state transition of Viterbi decoding, and reflects them in the metric, so that adaptive adjustment of the Viterbi decoding reference level is more effective without increasing the circuit scale. It is an object of the present invention to provide a maximum likelihood decoding method and a maximum likelihood decoding apparatus that can be realized in a simple manner.

In order to achieve the above-described object, the maximum likelihood decoding method according to the present invention provides each state transition t in the Viterbi decoder when performing maximum likelihood decoding in which bit information is detected from a reproduced signal using a Viterbi decoder. On the other hand, while storing two different reference levels v0 (t) and v1 (t), the metric m (t) for the state transition t when the signal s (n) for the time n is input is
m (t) = v0 (t) · (2 · s (n) −v1 (t))
It is characterized by including this term.

The maximum likelihood decoding apparatus of the present invention includes a Viterbi decoder that performs maximum likelihood decoding to detect bit information from a reproduced signal, and the Viterbi decoder has two different reference levels for each state transition t. v0 (t) and v1 (t) are stored, and the metric m (t) for the state transition t when the signal s (n) for the time n is input is as follows:
m (t) = v0 (t) · (2 · s (n) −v1 (t))
It has the means to perform the calculation comprised so that this term may be included.

  According to the maximum likelihood decoding method and the maximum likelihood decoding apparatus of the present invention, the metric m (t) for the state transition t is set to m (t) = v0 (t) · (2 · s (n) −v1 (t)). Since the calculation is performed using an arithmetic expression including a term and Viterbi decoding is performed, a partial response maximum likelihood decoding process in which the reference level is adaptively changed can be realized using an adder without using a multiplier. In particular, v0 (t) is a reference level given by a simple integer ratio for different t, and v1 (t) is more accurate than v0 (t), which can vary in the vicinity of v0 (t). When a high reference level is set and v0 (t) is a simple integer, (2 · s (n) −v1 (t)) can be calculated by bit shift and subtraction, so the accuracy of v1 (t) is increased. Even if adaptively changed, the calculation of m (t) can be executed only by addition / subtraction within v0 (t) +1 times, and there is an effect that appropriate maximum likelihood decoding can be realized with a simple configuration.

The embodiment of the present invention will be discussed by returning to the original metric equation m (t) = (q (n) −v (t)) ² described above. Here, since the problem is the reference level v (t), v (t) is divided into a part represented by a simple integer ratio and the remaining part.
v (t) = v0 (t) + δv (t)
At this time, the metric m ′ (t) with the criterion changed to m (k) is
m ′ (t) = ((v0 (t) −v0 (k)) + (δv (t) −δv (k)))
X (2q (n)-(v (t) + v (k))
It becomes. Here, the feature of this embodiment is the appearance of δv (t) −δv (k).
When the reference level is adaptively adjusted, the reason why the conventional simplification cannot be made is that this term does not become a simple integer (an integer of about one digit) ratio.

Therefore, an approximation is performed in which the first-order term of δv is discarded. This approximation method is not a mathematical approximation, but is not necessarily an exact approximation, because it is intended to simplify the circuit.
In this way, after all, the metric is
m ′ (t) = (v0 (t) −v0 (k)). (2q (n) − (v (t) + v (k))
It becomes.
Here, (v0 (t) −v0 (k)) is a simple integer because v0 (t) is represented by a simple integer ratio. Therefore, it can be seen that even if the accuracy of only the latter half of the right side of the above equation is increased, even if the adaptive change of the reference level can be realized, it is not necessary to use a multiplier.

As a result of summarizing the above, in the present embodiment, in the partial response maximum likelihood decoding method in which bit information is detected from a reproduction signal using a Viterbi decoder, two different reference levels with respect to the state transition t in the Viterbi decoder v0 (t), v1 (t) can be stored, and the metric for the state transition t is
m0 (t) = v0 (t) · (2 · r (n) −v1 (t))
An operation configured to include the term is performed. Here, v0 (t) can be expressed by a simple integer ratio, v1 (t) can be a value with higher accuracy than v0 (t), and v1 (t) is Thus, the equalization error of the corresponding state transition can be adaptively changed by negative feedback.

FIG. 1 is an explanatory view showing an embodiment of the present invention.
FIG. 1 is a block diagram showing an outline of a recorded information reproducing apparatus to which a maximum likelihood decoding method according to an embodiment of the present invention is applied.
This recorded information reproducing apparatus detects bit information by sampling a signal reproduced from, for example, a disk-shaped recording medium 1 as shown in the figure, and passes the signal recorded on the recording medium 1 through an optical pickup (not shown). A photodetector 2 to detect, a preamplifier 3 for amplifying the detection signal of the photodetector 2, a high-pass filter 4 and a low-pass filter 5 for filtering, an AD converter 6 for AD-converting and sampling these filter output signals, and an AD converter 6 And a waveform equalizer 7 and a PLL 8 for compensating for the phase and waveform of the reproduction signal obtained by the above, and a Viterbi decoder (partial response maximum likelihood decoder) 9 for decoding the data string from the sample string of the reproduction signal. Has been.

FIG. 2 is an explanatory diagram showing a state diagram of the Viterbi decoder according to this embodiment.
In this embodiment, the target response is PR (1221). Therefore, the state is represented by 3 bits and the state transition is represented by 4 bits. In FIG. 2, S (abc) represents the state abc. Each state includes an ACS (path metric addition comparison selection) block described later. Further, d / f in FIG. 2 represents a reference level corresponding to a transition bit and a state transition. The Viterbi decoder used in the present embodiment has a configuration in which an ACS circuit, which will be described later, is arranged on the wiring on the network shown in FIG.

FIG. 3 is a block diagram showing the ACS circuit of the Viterbi decoder according to the present embodiment.
This ACS circuit includes an ACS block 10 which is a size comparison part for comparing two or less path metrics to this state, and a path metric memory and a path memory based on the comparison result of the ACS block 10. The memory blocks 11 and 12 are parts to be updated, and the addition block 13 is a part to be updated by adding a metric to the path metric. The operation of the ACS block 10 for comparing path metrics is as follows.
s000; pm0000 <pm1000? ACS = 0: ACS = 1
s001; pm0001 <pm1001? ACS = 0: ACS = 1
s011; pm0011 ACS = 0
s111; pm0111 <pm1111? ACS = 0: ACS = 1
s110; pm0110 <pm1110? ACS = 0: ACS = 1
s100; pm1100 ACS = 1
Here, pm represents a path metric, and the path metric is a value obtained by integrating the metrics of paths that have been passed so far. A path refers to a state transition. Also here? The symbol of and: is a diversion of the C language notation, A? B: C represents the meaning of B if A, and C if not A. At this time, the meaning of the above equation is that when ACS = 0, the path memory and path metric from the path where the most significant bit is 0 are selected, and when ACS = 1, the path where the most significant bit is 1 It means to select the path memory and path metric from.

FIG. 4 is a block diagram showing a configuration of a calculation unit for calculating a metric input as the state transition metric shown in FIG. This calculation unit is prepared for each state transition, and is a main part of the present invention. The calculation unit includes a 1-bit shift register 21, a subtracter 22, and a v0 adder 23. It has a configuration that does not have. The subtractor 22 stores the Viterbi level v1 (t), and the v0 adder 23 stores the Viterbi level v0 (t).
In this calculation unit, the sample value q (n) of the input signal is doubled by the bit shift register 21 and the doubled signal is compared with the second reference level v1 (t) by the subtractor 22 to obtain the difference. This difference value is added by an integer | v0 (t) | representing the first reference level by the v0 adder 23 (however, if v0 (t) is a negative integer, the sign is inverted last) ). Thus, the metric m ′ (t) at the state transition t is output for the input signal q (n).
With this configuration, the numerical value stored in the last register is metric m ′ (t) = v0 (t) · (2 · q (n) −v1 (t))
It becomes. However, q (n) is a sample value of the nth input signal.

FIG. 5 is a block diagram showing a circuit example for adaptively changing the value of the second reference level v1 (t) in the calculation unit shown in FIG.
This circuit includes a 4-bit register 32 that stores bits output from the Viterbi decoder (PRML) 31, a delay unit 33 that delays a signal q (n) input to the Viterbi decoder, and a 4-bit register 32. A selector 34 that selects an output, a subtractor 35 that takes a difference between the output of the delay unit 33 and the second reference level v1 (t), and a multiplier 36 that multiplies the output of the subtractor 35 by the output of the selector 34. An adder 37 for adding the output of the multiplier 36 and the level error signal δv (t), and an adder 38 for adding the output of the adder 37 and the first reference level v0 (t). Have.

In other words, the signal q (n) input to the Viterbi decoder 31 and the continuous 4 bits x output from the Viterbi decoder 31 are input to this circuit, but the signal q (n) and the bit string x are A delay unit 33 adds a delay to q (n) so that the same timing is obtained.
Further, a first reference level v0 (t), a second reference level v1 (t), and a level difference δv (t) representing a difference between the first reference level and the second reference level are prepared as variables. Yes. However, v1 (t) and δv (t) are actually used as variables, and v0 (t) is fixed. Further, v1 (t) and δv (t) are updated every clock according to the clock.
First, the subtractor 35 calculates the difference between the input signal q (n) and the reference level v0 (t). On the other hand, the selector 34 determines whether x = t or not for the input continuous bit x. If x = t, the coefficient is set to ε, otherwise it is set to 0, and the product of this coefficient and the aforementioned difference is calculated by the multiplier 36. Here, ε is a predetermined minute coefficient. In the case of a digital circuit, it may be realized by means of shifting bits without using a multiplier.

The signal (equalization error) obtained as described above is added to the signal δv (t) accumulating the errors so far to update δv (t).
Finally, the updated δv (t) and the first reference level v0 (t) are added to obtain the updated second reference level v1 (t).
At this time, the operation of the circuit shown in FIG. 5 is expressed by the following equation. In the following expression, the subscript (t) indicating transition is omitted.
v1 (n + 1) = v0 (n) + δv (n)
δv (n + 1) = δv (n) + ε · δtx · (r (n) −v1 (n))
Here, n represents time. Also, δtx is a Kronecker δ which is 1 only when t = x.
By configuring the circuit as described above, the reference level can be adaptively adjusted.

It is a block diagram which shows the outline | summary of the recorded information reproducing | regenerating apparatus to which the maximum likelihood decoding method in the Example of this invention is applied. It is explanatory drawing which shows the state diagram of the Viterbi decoder by the Example shown in FIG. It is a block diagram which shows the ACS circuit of the Viterbi decoder by the Example shown in FIG. FIG. 4 is a block diagram showing a configuration of a metric calculation unit input as a state transition metric shown in FIG. 3. FIG. 5 is a block diagram showing a circuit example for adaptively changing the value of the second reference level v1 (t) in the calculation unit shown in FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Recording medium, 2 ... Photo detector, 3 ... Preamplifier, 4 ... High pass filter, 5 ... Low pass filter, 6 ... AD converter, 7 ... Waveform equalizer, 8 ... PLL, 9 ... Viterbi decoder.

Claims (10)

When performing maximum likelihood decoding that detects bit information using a Viterbi decoder from a reproduced signal,
For each state transition t in the Viterbi decoder, two different reference levels v0 (t), v1 (t) are stored and the state transition t when the signal s (n) for time n is input The metric m (t) for is
m (t) = v0 (t) · (2 · s (n) −v1 (t))
Is configured to include
And a maximum likelihood decoding method.   The maximum likelihood decoding method according to claim 1, wherein the v0 (t) with respect to the different state transitions t has a simple integer ratio relationship.   The maximum likelihood decoding method according to claim 1, wherein the v1 (t) is a value with higher accuracy than the v0 (t).   2. The maximum likelihood decoding method according to claim 1, wherein the v1 (t) is adaptively changed by negatively feeding back an equalization error of a reproduction signal of the corresponding state transition t.   The multiplication of v0 (t) · (2 · r (n) −v1 (t)) is performed by adding / subtracting (2 · r (n) −v1 (t)) by a smaller number of times than the integer | v0 (t) | The maximum likelihood decoding method according to claim 1, wherein A Viterbi decoder that performs maximum likelihood decoding to detect bit information from the reproduced signal;
The Viterbi decoder stores two different reference levels v0 (t) and v1 (t) for each state transition t, and the state transition when the signal s (n) for time n is input The metric m (t) for t is
m (t) = v0 (t) · (2 · s (n) −v1 (t))
Means for performing an operation configured to include
A maximum likelihood decoding apparatus characterized by the above.   7. The maximum likelihood decoding apparatus according to claim 6, wherein the v0 (t) with respect to the different state transitions t has a simple integer ratio relationship. The maximum likelihood decoding apparatus according to claim 6, wherein the v1 (t) is a value with higher accuracy than the v0 (t).   7. The maximum likelihood decoding apparatus according to claim 6, wherein v1 (t) is adaptively changed by negatively feeding back an equalization error of a reproduction signal of the corresponding state transition t.   The multiplication of v0 (t) · (2 · r (n) −v1 (t)) is performed by adding / subtracting (2 · r (n) −v1 (t)) by a smaller number of times than the integer | v0 (t) | The maximum likelihood decoding apparatus according to claim 6, wherein

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