JP3856704B2 - Metric margin extractor for maximum likelihood path - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an information recording / reproducing apparatus using maximum likelihood decoding such as Viterbi decoding, and more particularly to a circuit for obtaining a metric margin of a maximum likelihood path for detecting a margin of maximum likelihood decoding.
[0002]
[Prior art]
An error rate is often used as an evaluation value for measuring the decoding margin of Viterbi decoding. However, an evaluation value that can accurately measure the margin with a smaller number of samples than the error rate is called a maximum likelihood path metric margin. For example, Japanese Patent Application Laid-Open No. 10-21651 discloses a method of detecting a margin of a reproduced signal by statistically processing a metric margin called a difference metric and adjusting apparatus parameters.
[0003]
The metric margin of the maximum likelihood path is a metric margin related only to the maximum likelihood path among the metric margins related to selection of a surviving path in Viterbi decoding. When the value of the metric margin of this maximum likelihood path is negative, the maximum likelihood path follows an incorrect route and the decoding result becomes an error. Even when the value is positive, the signal margin is small. To do. That is, by using the metric margin of the maximum likelihood path, it is possible to determine whether the risk of error is large or small even if no error occurs in the decoding result. Therefore, the metric margin of the maximum likelihood path can be considered as a useful evaluation value that can grasp the decoding margin with a small sample amount.
[0004]
[Problems to be solved by the invention]
However, in order to obtain the metric margin of the maximum likelihood path described above, it is necessary to extract only the metric margin of the route through which the maximum likelihood path has passed from the metric margins that exist as many as the number of surviving paths. Therefore, there is a problem that if a system that performs this processing in real time by hardware is realized, the configuration becomes very complicated.
[0005]
The present invention has been made to solve the above-described problem, and provides a maximum likelihood path metric margin extraction circuit in Viterbi decoding that can extract a metric margin of a maximum likelihood path with a simple configuration. With the goal.
[0006]
[Means for Solving the Problems]
The invention according to the first aspect of the present invention is a maximum likelihood path metric margin extraction apparatus for extracting a metric margin related to a maximum likelihood path in a process of decoding reproduced data by Viterbi decoding. A metric margin calculating unit for calculating a metric margin in a related state transition, a metric margin calculated by the metric margin calculating unit, and a surviving path determination signal in Viterbi decoding, and extracting a metric margin of the maximum likelihood path Extracting means for selecting, from the metric margin calculated by the metric margin calculating means, a data selecting means for selecting a desired metric margin based on the surviving path determination signal, and data selection Data consisting of holding means for holding means selection results A plurality of selection holding means are configured to be connected corresponding to state transitions in Viterbi decoding, and the data selection holding means receives the selection result of the data selection means every time the survival path determination signal is received. The metric margin calculated by the metric margin calculating means is input to the first stage data selection holding means.
[0007]
Preferably, a metric margin held in the holding unit of the data selection holding unit after a predetermined number of stages may be output as a metric margin related to the maximum likelihood path.
[0008]
In Viterbi decoding processing of reproduced data, a path memory in which a plurality of decoded data selection / holding circuits for selecting and holding temporary decoded data is connected is used to calculate the maximum likelihood path metric. The likelihood path metric margin extraction device outputs the metric margin held in the holding means of the data selection holding means in the same stage as the stage in which the decoded data is output in the path memory as the metric margin related to the maximum likelihood path. May be.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
[First Embodiment]
Hereinafter, an optical disk apparatus using a maximum likelihood path metric margin extraction circuit in the Viterbi decoding according to the first embodiment of the present invention will be described. Needless to say, the present invention is not limited to an optical disc apparatus, and can be applied to all information reproducing apparatuses that perform maximum likelihood decoding such as Viterbi decoding. In addition, the following description describes a circuit configuration according to a specific condition, but the present invention is not limited to the configuration described in the following embodiments, and only by the description of the appended claims. Needless to say, it is specified.
[0010]
In the following embodiments, a so-called PRML (Partial Response Maximum Likelihood) detection method is adopted in which maximum likelihood decoding is performed by a Viterbi decoder etc. on the assumption that reproduced data is equalized to a partial response method. . This partial response characteristic is a PR (1, 2, 1) characteristic, and a Run-Length-Limited code such as an RLL (1, 7) code is used, and the minimum inversion interval is limited to 2.
[0011]
The PR (1, 2, 1) characteristic is as follows. Assume that a 1-bit rectangular signal as shown in FIG. At this time, it is assumed that the waveform after passing through the transmission line spreads to the sampling position of the adjacent bits as shown in FIG. 1B, and the amplitude ratio becomes 1: 2: 1. The PR (1, 2, 1) characteristic means such a case. In the optical disk apparatus described below, assuming that the transmission path means from the optical disk 31 to immediately before the Viterbi decoder, reproduction data in the case of reproducing 1 bit of isolated recording data by the PR (1, 2, 1) characteristic. The amplitude ratio of each sample point is 1: 2: 1.
[0012]
The minimum inversion interval of 2 means the following. That is, when considering the data before passing through the transmission path (recorded data on the disc in the case of an optical disc apparatus), the minimum inversion interval is 2 when the continuous number of 0 or 1 is at least 2. That is, it means that there is no data continuous with “0, 1, 0” (the continuous number of 1 is 1) or data continuous with “1, 0, 1” (the continuous number of 0 is 1).
[0013]
Here, the description of the concept of Viterbi decoding will be supplemented. It is assumed that the reproduction data has PR (1, 2, 1) characteristics and the minimum inversion interval is 2. Assuming that the transmission path (pickup, equalization circuit, etc.) that generates this data string is a virtual encoder that encodes recorded data, the state transition diagram of this encoder is expressed as shown in FIG. The
[0014]
Referring to FIG. 2, the encoder can take four states, S00, S01, S10 and S11. The state S00 means that the recorded data is continuous with “0, 0”. Similarly, the states S01, S10, and S11 mean that the recording data is continuous with “0, 1”, “1, 0”, and “1, 1”, respectively. Here, the minimum inversion interval is limited to 2. For this reason, there is no recording data continuous with “0, 1, 0” or “1, 0, 1”. Therefore, there cannot be a transition from the state S10 to the state S01 and a transition from the state S01 to the state S10.
[0015]
In FIG. 2, the values attached to the arrows indicating the respective superordinate bodies are expected values on the right side and decoded data on the left side. Here, the “expected value” is reproduction data when superimposed in correspondence with recorded data in consideration of the above-described PR (1, 2, 1) characteristics, and there is no noise superposition or distortion at all. Is ideal reproduction data. For example, the state transition to S00-S01 in FIG. 2 is when the recorded data is continuous with “0, 0, 1”, and “1 | d1” attached to the figure is expected to be 1 at that time. It represents that the value is d1.
[0016]
When PR (1, 2, 1) and the minimum inversion interval are 2 as in this example, there are four types of expected values: d0, d1, d3, and d4. The actual expected value depends on the word width of the system. For example, if the reproduction data has a value of 0 to 255 with an 8-bit width, d0, d1, d3, and d4 are 64, 96, 160, 192, and the like, respectively.
[0017]
The state transition diagram shown in FIG. 2 is expanded in the time axis direction and is called a trellis diagram. An example is shown in FIG. The arrows in FIG. 3 represent state transitions and are called “branches”. Each branch is accompanied by decoded data and an expected value in the same manner as the state transition in the state transition diagram described above, and indicates this in the form of “decoded data | expected value”.
[0018]
The square of the difference between the expected value and the reproduction data actually input to the Viterbi decoder is called “branch metric”. The branch metric represents how “probable” the decoded data associated with the branch is when the superimposed noise is assumed to be white Gaussian noise. In the example shown in FIG. 3, there are six branches for each sample. Therefore, there are six branch metrics for each sample. However, in this example, since branches d1 and d3 having the same expected value exist, there are four types of branch metrics for each sample. It should be noted that any amount that represents the “probability” of the decoded data can be used as a branch metric even if it conforms to a definition other than the above-described branch metric definition.
[0019]
A route that follows a branch of the trellis diagram as shown in FIG. 3 is called a “path”. The sum of branch metrics of all past branches of the path is called “path metric”. Maximum likelihood decoding is to calculate which path metric is the smallest among all the paths that have a huge number of combinations in this trellis diagram, and is called "maximum likelihood path". A path is determined, and decoded data associated with each branch of the maximum likelihood path is used as a decoded data string. Viterbi decoding is a method for efficiently determining the maximum likelihood path without scanning all paths in which such a large number of combinations exist.
[0020]
In this method, for example, referring to FIG. 3, the path metrics of the two paths that have transitioned to the state S00 are compared and the smaller one is left, and the path metrics of the two paths that have transitioned to the state S11 are similarly determined. Leave the smaller one in comparison. In this way, it is possible to delete a path metric with the smallest path metric at an early stage and obtain a path with the smallest path metric without considering all of the enormous combinations.
[0021]
The remaining path in the path metric comparison is called a “surviving path”. In the example illustrated in FIG. 3, there are four surviving paths at each time including the paths that have transitioned to the states S01 and S10.
[0022]
Referring to FIG. 4, the optical disk apparatus according to this embodiment includes a spindle motor 32 for rotating optical disk 31, an optical pickup 33 for converting recording data recorded on optical disk 31 into an electrical signal, and the like. Based on the electrical signal output from the low pass filter (LPF) 34 for removing the high frequency noise of the electrical signal output from the optical pickup 33 and the electrical signal output from the LPF 34, a channel clock signal synchronized with the recording data is generated. PLL (Phase Lock Loop) 35 for distributing to each block.
[0023]
The optical disk apparatus further includes an AD (Analog-to-Digital) converter 36 for quantizing the output of the LPF 34 at a sampling timing determined by a channel clock signal supplied from the PLL circuit 36, and an AD converter 36 for quantizing the output. And an equalization circuit 37 for equalizing the processed data. The output of the equalization circuit 37 is hereinafter referred to as “reproduction data”.
[0024]
The optical disc apparatus further receives the reproduction data output from the equalization circuit 37, performs maximum likelihood decoding, and outputs the decoded data, a surviving path determination signal generated in the Viterbi decoding process as will be described later, and a metric margin. A Viterbi decoder 38 for receiving, a survivor path determination signal output from the Viterbi decoder 38 and a metric margin, and extracting a metric margin related only to the maximum likelihood path and sending it to a host device (not shown) A metric margin extraction circuit 39 for the path. The decoded data output from the Viterbi decoder 38 is also sent to a host device (not shown).
[0025]
A host device (not shown) grasps the decoding margin of decoded data using the metric margin from the metric margin extraction circuit 39 of the maximum likelihood path, and changes the parameters of the device.
[0026]
Note that the AD converter 36, the equalization circuit 37, the Viterbi decoder 38, and the metric margin extraction circuit 39 for the maximum likelihood path all receive the channel clock signal output from the PLL circuit 35, and in units of clocks of the channel clock signal. It is a digital circuit that operates.
[0027]
Referring to FIG. 5, the Viterbi decoder 38 shown in FIG. 4 determines a branch metric calculation unit 100 that calculates six branch metrics based on reproduction data, and determines a surviving path based on the six branch metrics. The S00 survivor path determination signal that is the survivor path determination signal in the S00 state and the S11 survivor path determination signal that is the survivor path determination signal in the S11 state are output, and the metric margin in the S00 state S00 metric margin and S11 metric margin that is a metric margin in the S11 state are calculated and output, and a survivor path determination unit 102, an S00 survivor path determination signal, and an S11 survivor path determination signal are received and decoded. And a path memory 60 for generating data.
[0028]
Referring to FIG. 6, branch metric calculator 100 includes branch metric calculators 21-26 for receiving reproduction data and calculating a branch metric for state transitions as shown below.
[0029]
Branch metric calculator 21: S11 → S11
Branch metric calculator 22: S01 → S11
Branch metric calculator 23: S11 → S10
Branch metric calculator 24: S00 → S01
Branch metric calculator 25: S10 → S00
Branch metric calculator 26: S00 → S00
Referring to FIG. 7, surviving path determination unit 102 includes registers 217-220 for holding path metrics described below.
[0030]
Register 217: Metric of surviving path that has transitioned to state S11
Register 218: Metric of surviving path that has transitioned to state S10
Register 219: Metric of surviving path that has transitioned to state S01
Register 220: Metric of surviving path that has transitioned to state S00
The survivor path determination unit 102 further includes an adder 27 for adding the output of the branch metric calculator 21 and the output of the register 217, and an adder for adding the output of the branch metric calculator 22 and the output of the register 219. 28, an adder 29 for adding the output of the branch metric calculator 23 and the output of the register 217, an adder 210 for adding the output of the branch metric calculator 24 and the output of the register 220, and a branch metric calculation An adder 211 for adding the output of the register 25 and the output of the register 218; and an adder for adding the output of the branch metric calculator 26 and the output of the register 220 212 Including.
[0031]
The survival determination unit 102 further compares the output of the adder 27 (S11 → S11 path metric) with the output of the adder 28 (S01 → S11 path metric) and indicates the smaller S11 survival path determination signal. , The output of the adder 27 and the output of the adder 28 are received, the input corresponding to the path indicated by the S11 survivor path determination signal is selected, and the register 217 The selector 213 for giving as a path metric of the path, the output of the adder 211 (path metric of S10 → S00) and the output of the adder 212 (path metric of S00 → S00) are compared, and S00 indicating the smaller one In response to the comparator 215 for outputting the surviving path determination signal, the output of the adder 211 and the output of the adder 212, the S00 surviving path determination signal And a selector 216 for providing the register 220 selects the input of the direction corresponding to the path that is more indicated as the path metric for the survivor path.
[0032]
The output of the adder 29 (S11 → S10 survival path path metric) and the output of the adder 210 (S00 → S01 survival path path metric) are connected to registers 218 and 219, respectively.
[0033]
The survivor path determination unit 102 further receives the output of the adder 27 (S11 → S11 path metric) and the output of the adder 28 (S01 → S11 path metric), and determines the survivor path in S11. A metric margin calculator 224 for calculating the S11 metric margin that is the difference between the path metrics of the two paths to be compared, the output of the adder 211 (S10 → S00 path metric), and the output of the adder 212 (S00) → a metric margin calculator 227 for calculating an S00 metric margin which is a difference between path metrics of two paths to be compared when determining a surviving path in S00. .
[0034]
The metric margin calculator 224 calculates the absolute value of the subtractor 222 for subtracting the output of the adder 28 from the output of the adder 27 and the output of the subtractor 222 and outputs the result as an S11 metric margin. And an arithmetic unit 223. The metric margin calculator 227 calculates the absolute value of the subtracter 225 for subtracting the output of the adder 211 from the output of the adder 212 and the output of the subtractor 225 and outputs the absolute value as the S00 metric margin. And an arithmetic unit 226.
[0035]
Since the Viterbi decoder itself has no error detection capability, the metric margin should never be a negative value and should always be a positive value. Therefore, when calculating the difference between two path metrics, the smaller one should be subtracted from the larger one, but in this embodiment, the absolute value of the subtraction result is obtained without considering the subtraction direction. Therefore, the metric margin is set to a positive value. However, it goes without saying that the subtraction direction may be controlled using the comparison results of the comparators 214 and 215.
[0036]
Referring to FIG. 8, path memory 60 shown in FIG. 5 includes a plurality of selection holding circuits 110 connected to receive the S11 surviving path determination signal and the S00 surviving path determination signal. Each selection holding circuit 110 receives four outputs from the selection holding circuit in the preceding stage, and selects the four signals whose values are determined by the S11 survival path determination signal and the S00 survival path determination signal in the subsequent stage. They are connected in series so as to be supplied to the holding circuit. Four flip-flops 121 to 124 are provided in the preceding stage of the head selection holding circuit 110. These flip-flops 121-124 are given fixed values of “1”, “0”, “1”, “0”, respectively, and the outputs of these flip-flops 121-124 are sent to the leading selection holding circuit 110. Given as input. Although this fixed value is not actual decoded data, it is handled in the same way as decoded data in the subsequent processing, and is referred to as “temporary decoded data” in this specification.
[0037]
Each selection / holding circuit 110 receives the outputs of the S11 selection / holding circuit 47 that operates according to the S11 surviving path determination signal, the S00 selection / holding circuit 410 that operates according to the S00 remaining / surviving path determination signal, and the S11 selection / holding circuit 47 of the preceding stage. It includes a flip-flop 42 and a flip-flop 43 that receives the output of the preceding S00 selection / holding circuit 410. In the head selection holding circuit 110, the S11 selection holding circuit 47 and the flip-flop 42 are connected to receive the output of the flip-flop 121, and the S00 selection holding circuit 410 and the flip-flop 43 are connected to receive the output of the flip-flop 124. .
[0038]
The S11 selection and holding circuit 47 is a SEL that receives a first input A that receives the output of the preceding S11 selection and holding circuit 47, a second input B that receives the output of the preceding flip-flop 43, and an S11 survivor path determination signal. In order to select and output input A when S11 → S11 survives the determination and input B when S01 → S11 according to the value of the S11 surviving path determination signal, respectively. And a flip-flop 46 for holding the output of the selector 47 and supplying it to the subsequent S11 selection and holding circuit 47 and the flip-flop 42.
[0039]
The S00 selection / holding circuit 410 is a first input A that receives the output of the preceding S00 selection / holding circuit 410, a second input B that receives the output of the preceding flip-flop 42, and a SEL that receives the S00 surviving path determination signal. To select and output input A when S00 → S00 survives the determination, and input B when S10 → S00, according to the value of the S00 surviving path determination signal. And a flip-flop 49 for holding the output of the selector 48 and supplying it to the subsequent S00 selection / holding circuit 410 and the flip-flop 43.
[0040]
According to the path memory 60 connected in this way, depending on the determination result of the surviving path, the data held in the previous flip-flop is shifted as it is like a shift register, or the value of another row is shifted. It is determined whether it will be copied. Therefore, when data passes through a certain number of stages, the values of the flip-flops in the four rows are all the same. Therefore, if any one of the last four flip-flops is output as decoded data, decoded data corresponding to the maximum likelihood path is generated.
[0041]
Here, consider the case where a decoding error occurs even when Viterbi decoding is performed. In the Viterbi decoder shown in FIG. 5 to FIG. 8, a decoding error occurs when the determination is incorrect when the path metrics of the two paths are compared by the comparators 214 and 215. The reason why the determination is wrong is because, for example, noise or the like is superimposed on the reproduction data. Therefore, if the determination is not incorrect, the difference between the path metrics of the two paths to be compared represents a margin for preventing a decoding error during decoding. The “metric margin” described so far means a difference in path metrics between paths that have transitioned to the same state as described above.
[0042]
Note that the condition under consideration is that the minimum inversion interval is 2, so there is only one path that transitions to states S10 and S01. Therefore, in this case, the surviving path is determined unconditionally. At this time, the metric margin can be considered infinite. As shown in FIG. 7, the Viterbi decoder of this embodiment is different from the conventional apparatus in that metric margin calculators 224 and 227 are provided.
[0043]
Now, no matter how efficiently the Viterbi decoder erases paths, there are always four surviving paths. Two metric margins are calculated for each sample, and there are four metric margins for each sample, taking into account the metric margins related to S10 and S01 that have an infinite value. However, since only the metric margin relating to the maximum likelihood path is used as the evaluation value of the reproduction signal, the remaining three metric margins are unnecessary. For example, if the arrow indicated by the solid line in the trellis diagram of FIG. 3 is the maximum likelihood path, only the metric margin in the state surrounded by the dotted circle is important.
[0044]
However, in order to determine the maximum likelihood path in Viterbi decoding, reproduction data in the future from the present time must be taken into account, and therefore the work of extracting the metric margin of the maximum likelihood path is quite complicated as hardware. . In the apparatus according to the present embodiment, the maximum likelihood path metric margin is extracted by the maximum likelihood path metric margin extraction circuit 39 shown in FIG.
[0045]
Referring to FIG. 9, metric margin extraction circuit 39 for the maximum likelihood path is provided in association with S11, and a metric margin calculation circuit for holding and shifting a metric margin calculated as described later with respect to state S11. S11 line, S10 line similarly provided in relation to S10, S01 line provided in relation to S01, and S00 line provided in relation to S00. These S11 line, S10 line, S01 line, and S00 line all include multi-stage registers (first to n stages) that hold data in units of words connected to each other in a connection form corresponding to state transition in Viterbi decoding. Details thereof will be described below.
[0046]
First, the S10 line and the S01 line respectively include a plurality of registers 5 and 6 that hold data in units of words connected as described below. The first-stage registers 5 and 6 are connected so that a fixed value “FF” (hexadecimal) is given. This value corresponds to the infinite metric margin described above. The circuit that gives this fixed value “FF” (hexadecimal) outputs a fixed value, but it can also be considered to calculate and output a metric margin when a surviving path is determined unconditionally. . The registers 5 on and after the second stage are connected so as to receive the output of the S11 line in the previous stage. Further, the second and subsequent registers 6 are connected so as to receive the output of the S00 line in the previous stage.
[0047]
The first stages of the S11 line and the S00 line include registers 4 and 7 that are connected to receive the S11 metric margin and the S00 metric margin, respectively, and hold word unit data.
[0048]
Each of the second and subsequent stages of the S11 line includes a data selection / holding circuit 10 connected to receive the output of the previous S11 line and the output of the register 6 of the previous S01 line. The data selection / holding circuit 10 has an input A that receives the output of the preceding S11 row, an input B that receives the output of the register 5 of the preceding S01 row, and a SEL input that receives the S11 surviving path determination signal in the state S11. When the S11 surviving path determination signal indicates that the S11 → S11 path has survived, the input A data is indicated. When the S11 → S11 path has survived, the input B data is indicated. A data selector 8 that selects and outputs data in units of words, and a register 9 that holds the output of the data selector 8 in units of words and outputs it to the subsequent stage. The output of the register 4 is connected to the input A of the data selector 8 at the second stage, and the output of the register 6 at the first stage is connected to the input B, respectively.
[0049]
Each stage after the second stage of the S00 line includes a data selection / holding circuit 13 connected to receive the output of the previous S00 line and the output of the S10 line. The data selection / holding circuit 13 has an input A that receives the output of the previous S00 row, an input B that receives the output of the register 5 of the previous S10 row, and a SEL input that receives the S00 survival path determination signal in the state S00. If the S00 surviving path determination signal indicates that the S00 → S00 path survives, the input A data is indicated. If the S00 → S00 path indicates that the surviving path is determined, the input B data is indicated. A data selector 11 that selects and outputs data in units of words, and a register 12 that holds the output of the data selector 11 in units of words and outputs it to the subsequent stage. The output of the register 7 is connected to the input A of the data selector 11 at the second stage, and the output of the register 5 at the first stage is connected to the input B, respectively.
[0050]
The connection relationship between the input and output of the multistage register in the metric margin extraction circuit 39 of the maximum likelihood path corresponds to the state transition shown in FIG.
[0051]
When the surviving path is determined unconditionally, it is unconditionally determined which output of the previous stage is selected, so that the connection form in which the output of a specific register is always unconditionally selected is obtained. Things like the data selectors 8 and 11 are unnecessary. However, a connection that always selects the output of a fixed register without using a data selector is one form of selection.
[0052]
[Operation of Metric Margin Extraction Circuit 39 for Maximum Likelihood Path]
The maximum likelihood path metric margin extraction circuit 39 having the above-described configuration operates as follows. When the registers of the metric margin extraction circuit 39 of the maximum likelihood path are arranged in a predetermined n stages (for example, about n = 20), S11 line Focusing on the following, the following operation is performed. When the S11 survivor path determination signal indicates that S11 → S11 has survived, the S11 line shifts to copy the metric margin data held in the register 9 of the previous S11 line to its own register 9 Performs register operation. On the other hand, if the S11 surviving path determination signal indicates that S01 → S11 survived, the S11 line copies the metric margin data held in the register 6 of the preceding S01 line to its own register 9 The operation to perform is performed.
[0053]
Similarly, focusing on the S00 line, the following operation is performed. When the S00 surviving path determination signal indicates that S00 → S00 has survived, the S00 line is a shift register that copies the metric margin data held in the register 12 of the preceding S00 line to its own register 12 Perform the action. On the other hand, if the S00 surviving path determination signal indicates that S10 → S00 survived, the S00 line copies the metric margin data held in the register 5 of the preceding S10 line to its own register 12. Perform the action.
[0054]
Since such an operation is performed, when the metric margin data has passed a certain number of stages, the registers 9, 5, 6, and 12 included in the S11, S10, S01, and S00 lines all have the same value of metric margin data. Will be stored. This value is the metric margin data of the maximum likelihood path. Therefore, the metric margin of the maximum likelihood path can be obtained by outputting the data of one of the four registers at the final stage (in this embodiment, the final stage register 12 of the S00 row).
[0055]
The metric margin extraction circuit 39 for the maximum likelihood path has a configuration similar to the path memory 60 described above. However, the metric margin extraction circuit 39 of the maximum likelihood path can extract only the metric margin of the maximum likelihood path from the metric margin of each surviving path by using the selection target data as the metric margin. As described above, it is complicated to implement such processing by hardware, but this can be realized by a simple circuit with the above-described configuration.
[0056]
[Second Embodiment]
FIG. 10 is a block diagram of a partial circuit of the optical disc apparatus according to the second embodiment. Referring to FIG. 10, this circuit includes a Viterbi decoder 81 including path memory 82 having the same configuration as that described in the first embodiment, and a surviving path determination output from Viterbi decoder 81. A configuration similar to that described in the first embodiment for calculating the metric margin of the maximum likelihood path based on the signal and the metric margin, and having the same number of stages as that of the selection holding circuit in the path memory 82 A maximum likelihood path metric margin extraction circuit 83 having a multistage register, and a predetermined pattern is detected from the decoded data string output from the path memory 82, and the metric margin of the predetermined pattern in the maximum likelihood path metric margin data string is obtained. A pattern matching circuit 84 for outputting a coincidence detection signal serving as a marker signal to be pointed, and a method for outputting the coincidence detection signal. By using Kkumajin, including for the evaluation process by extracting only metric margin in a predetermined pattern, and a metric margin evaluation circuit 85 of the maximum likelihood path.
[0057]
The number of stages of the path memory 82 is normally set to a minimum number of stages sufficient for determining the maximum likelihood path. Therefore, it is appropriate to use this number of stages as the number of stages of the multistage register of the metric margin extraction circuit 83 of the maximum likelihood path. Therefore, by adopting the configuration shown in the second embodiment, it can be expected that the decoded data and the metric margin can be synchronized without increasing redundant parts on the system.
[0058]
The output of the path memory 82, that is, the output of the decoding result of the Viterbi decoder 81 and the output of the maximum likelihood path metric margin extraction circuit 83 are synchronized with each other. Therefore, by using the timing when the pattern matching circuit 84 detects a predetermined pattern from the decoded data string output from the path memory 82, only the metric margin in the predetermined pattern in the maximum likelihood path is extracted and processed. Can do. As a result, it is possible to easily obtain an evaluation value for adjusting a parameter having high sensitivity to the metric merge of the predetermined pattern.
[0059]
[Another example of metric margin extraction circuit for maximum likelihood path]
The maximum likelihood path metric margin extraction circuit 39 shown in FIG. 9 includes registers 4-7 arranged at the first stage of each row. However, the configuration of the maximum likelihood path metric margin extraction circuit is not limited to such an example. For example, the configuration may be such that all the registers 4-7 in the first stage are removed. Alternatively, only the first-stage registers 5 and 6 may be removed.
[0060]
Apart from this, the following configuration may be considered in order to align the hardware configuration of each stage of the metric margin extraction circuit of the maximum likelihood path. FIG. 11 shows the configuration of the metric margin extraction circuit 130 for the maximum likelihood path in this modification. The maximum likelihood path metric margin extraction circuit 130 is different from the maximum likelihood path metric margin extraction circuit 39 in that the data in the second and subsequent stages is replaced with the register 4 in the S11 line of the maximum likelihood path metric margin extraction circuit 39. A data selection and holding circuit 13 having the same configuration as the data selection and holding circuit 11 in the second and subsequent stages is used instead of the register 7 in the S00 row in that the data selection and holding circuit 10 having the same configuration as the selection and holding circuit 10 is arranged. It is a point that is arranged. However, the S11 metric margin is given to each of the two inputs of the data selector 8 of the first-stage data selection and holding circuit 10, and the two inputs of the data selector 11 of the first-stage data selection and holding circuit 13 are In any case, the S0 metric margin is given, which is different from the data selection holding circuit in the other stage.
[0061]
Note that the hardware configuration of the S10 and S01 lines can be the same as that of the S11 and S00 lines. In this case, the two inputs of the data selector in each data selection / holding circuit in the row S10 are supplied with the output of the register 9 in the previous S11 row, and the data selectors in each data selection / holding circuit in the row S01. The two inputs are given the output of the register 12 in the preceding S00 line.
[0062]
Further, a circuit having the same configuration as that of the data selection holding circuits 10 and 13 may be provided in place of the registers 5 and 6 only at a specific stage, for example, the first stage. In this case, the same data may be given to the two inputs of each data selector. In short, any hardware configuration may be used as long as a metric margin of a path corresponding to a path determined to be a surviving path is selected and propagated to the subsequent stage.
[0063]
As mentioned above, although embodiment of this invention has been described in detail, it cannot be overemphasized that this invention can be implemented with a various form besides having mentioned above. For example, each of the data selectors 10 and 13 used in the above description has two inputs. However, instead of this, a data selector having three or more inputs can be adopted depending on the application. In the above description of the embodiment, it is assumed that the encoder performs state transition in accordance with the state transition diagram shown in FIG. 2, but the encoder state transition is not limited to that shown in FIG. Of course, the trellis diagram may be different from that shown in FIG.
[0064]
The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
[0065]
【The invention's effect】
As described above, according to the present invention, a desired metric margin is selected based on the surviving path determination signal in Viterbi decoding, and the selected metric margin is shifted in accordance with the state transition in Viterbi decoding. As a result, in the Viterbi decoding process, the metric margin of the maximum likelihood path can be extracted from the metric margin associated with each surviving path by using a simple configuration extraction unit.
[0066]
Since the metric margin held in the holding means of the data selection holding means after the predetermined number of stages becomes the same value, any of them may be output as the metric margin related to the maximum likelihood path, and the circuit can be configured flexibly. Can do.
[0067]
Path memory and metric margin extraction by outputting the metric margin held in the data selection holding means in the same stage as the stage where the decoded data is output in the path memory as the metric margin related to the maximum likelihood path The circuit has the same configuration, and the circuit can be simplified.
[Brief description of the drawings]
FIG. 1 is a waveform diagram for explaining a partial response characteristic.
FIG. 2 is a state transition diagram for explaining the concept of Viterbi decoding.
FIG. 3 is a trellis diagram for explaining the concept of Viterbi decoding.
FIG. 4 is a block diagram of an optical disc apparatus according to an embodiment of the present invention.
FIG. 5 is a block diagram showing a configuration of a Viterbi decoder according to an embodiment of the present invention.
FIG. 6 is a block diagram illustrating a configuration of a branch metric calculation unit.
FIG. 7 is a block diagram illustrating a configuration of a surviving path determination unit.
FIG. 8 is a block diagram showing a configuration of a path memory.
FIG. 9 is a block diagram showing a configuration of a maximum likelihood path metric margin extraction circuit for extracting a maximum likelihood path branch metric margin according to the first embodiment;
FIG. 10 is a block diagram showing a configuration of a Viterbi decoder employing a maximum likelihood path metric margin extraction circuit according to the second embodiment.
FIG. 11 is a block diagram showing another configuration of the metric margin selection shift circuit.
[Explanation of symbols]
4-7, 9, 12, 217-220 Register, 8, 10, 11, 13 Data selector, 21-26 Branch metric calculator, 27-29, 210-212 Adder, 31 Optical disc, 32 Spindle motor, 33 Optical pickup, 34 low-pass filter, 35 PLL circuit, 36 AD converter, 37 equalization circuit, 38 Viterbi decoder, 39,83 Maximum likelihood path metric margin extraction circuit, 60 path memory, 81 Viterbi decoder, 82 path memory 84 pattern matching circuit, 85 maximum likelihood path metric margin evaluation circuit, 100 branch metric calculation unit, 102 surviving path determination unit, 222,225 subtractor, 223,226 absolute value calculation unit, 213,216 selector, 224 , 227 Metric margin calculator, 214, 215 comparator.

Claims (3)

A metric margin extraction device for a maximum likelihood path for extracting a metric margin related to a maximum likelihood path in a process of Viterbi decoding reproduction data,
Metric margin calculating means for calculating a metric margin in a state transition related to the Viterbi decoding;
Receiving a metric margin calculated by the metric margin calculating means and a surviving path determination signal in Viterbi decoding, and including an extracting means for extracting a metric margin of the maximum likelihood path,
The extraction means includes
Data selection means for selecting a desired metric margin from metric margins calculated by the metric margin calculation means based on a surviving path determination signal; and holding means for holding a selection result of the data selection means; A plurality of data selection holding means consisting of connected in correspondence with the state transition in the Viterbi decoding,
The data selection holding means has a function of shifting the selection result of the data selection means to the subsequent data selection holding means every time the survival path determination signal is received,
The metric margin calculated by the metric margin calculating means is input to the data selection holding means in the first stage ,
The metric margin of the maximum likelihood path is processed in words ,
The said data selection holding means of the first stage, when the survivor path is determined unconditionally, the value corresponding to the word a value corresponding to the infinite metric margin are entered as the metric margin, Maximum margin metric margin extractor.   The metric margin extraction of the maximum likelihood path according to claim 1, wherein the metric margin held in the holding means of the data selection holding means after a predetermined number of stages is output as a metric margin related to the maximum likelihood path. apparatus. In the Viterbi decoding process of the reproduction data, a path memory in which a plurality of decoded data selection holding circuits for selecting and holding temporary decoded data is connected is used to calculate the metric of the maximum likelihood path,
The maximum likelihood path metric margin extraction apparatus uses the metric margin held in the holding means of the data selection holding means in the same stage as the stage in which the decoded data in the path memory is output, as the metric margin related to the maximum likelihood path. The metric margin extraction device for the maximum likelihood path according to claim 1, wherein:

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