JP3858362B2 - Decoding apparatus and method, and data reproducing apparatus - Google Patents

Description

【００２７】
なお、式（１）〜式（７）においては、入力スイッチ２１で選択された連続する２サンプルの値をｚ₁ ，ｚ₂ 、振幅基準レベルをＲとする。
【００２８】
次に、最尤パスメトリック選択回路２３において、式（８）〜式（１３）に示す規則にしたがって最尤ブランチが選択され、パスメトリックがラッチ２４によってラッチされる。
【００２９】
【数２】

【００３０】
最尤ブランチを選択した結果は、パスメモリ２５に送られ、パスメモリ２５でその情報から生き残りパスを１つに絞る処理が行われる。
【００３１】
生き残りパスと判断されたパスは、検出データとして出力され、切り替え回路部４０からの切り替え信号に基づいて、合成回路５０で第２の処理回路部３０からの出力信号と合成され、偶数／奇数系列が合成されたデータがビタビデコーダ１８より出力される。
【００３２】
図５に、パスメモリ部分の詳細なブロック図を示す。
パスメモリ２５は、符号語長に等しい１０ビットの長さをもつローカルパスメモリ２５１と、同じく１０サンプルを単位としてシフトするグローバルパスメモリ２５２₁ 〜２５２_-6，２５３₁ 〜２５３_-6，２５４₁ 〜２５４_-6を有する。
ローカルパスメモリ２５１は、パラレルロード／シリアルシフトレジスタによって構成され、最初の１０サンプルの生き残りパスを決定し、各状態ごとに１０ビット単位で出力する。生き残りパスは、グローバルバスメモリによってシフトされ、最終的にセレクタ２５５によって最尤パスが選択され出力される。
状態数は６であるから、１０サンプル前の状態は３ビットのデータで表現することができ、これはラッチ２５６₁ 〜２５６_-6およびラッチ２５７₁ 〜２５７_-6によってシフトされる。
セレクタ２５９の出力は２０サンプル前の状態を表し、セレクタ２５８の出力は３０サンプル前の状態を表すので、セレクタ２５５の出力は３０サンプル前の生き残りパスを表し、これが復号データとして出力される。
【００３３】
チャネル復号化部１９は、ビタビデコーダ１８で復号化された信号に基づいて、基のデジタル信号に変換し、ハードディスクコントローラに出力する。
【００３４】
次に、磁気ディスク装置１の動作についてまとめて説明する。
磁気ディスク装置１においては、記録対象のデータが図示せぬハードディスクコントローラから入力され、チャネル符号化部１１によってチャネル符号に変調され、記録アンプ１２を介して図示せぬ記録ヘッドより磁気ディスク媒体８０に記録される。
【００３５】
そして、磁気ディスク媒体８０より図示せぬ再生ヘッドにより再生された信号は、再生アンプ１３で増幅されてＡ／Ｄ変換部１４によりデジタル信号に変換され、等化器１５によってＰＲ４の特性の信号に等化される。この時等化された信号ｙ_k は、６ビットの２の補数によって表現されており、−３２≦ｙ_k ≦＋３１の値をとる。
また、この等化された信号に基づいて、ＰＬＬ回路１６によってクロックが生成される。
等化された信号は、非線形量子化器１７によって離散した値に丸められた後、ビタビデコーダ１８によってデコードされ、チャネル復号化部１９により元の信号に復元され、図示せぬハードディスクコントローラを経由して出力される。
【００３６】
次に、このような磁気ディスク装置１によって、すなわち、ビタビデコーダ１８によるデコードの前に非線形量子化器１７を設け、図２に示したようなパタンに基づいた非線形量子化を行うことによって、検出特性が劣化しないこと、および、これにより消費電力が削減できることについて、図６〜図８を参照して説明する。
ＰＲ４等化を使用する系では、信号の存在点は｛−１，０，＋１｝の３値となる。
ＰＲ４に等化されたサンプル値を６ビット幅で表現し、＋１の信号増幅が＋１６となるように振幅を調整すると、信号の存在点は｛−１６，０，＋１６｝と表現できる。
実際には、等化誤差やノイズの影響により、サンプル値は信号存在点の周囲にほぼガウス分布となるように分布する。
【００３７】
磁気記録系からの再生信号をＰＲ４等化したサンプル列の分布を図６に示す。図６において、●印は実験値、破線はガウス分布を示す曲線である。図６示すように、前述したように、｛−１６，０，＋１６｝のどのレベルとも、ほぼガウス分布となっている。
このように、磁気記録系からの再生信号をＰＲ４に等化したサンプル列は、信号点付近にそのほとんどが偏在し、たとえば±８付近や±２４以上の領域などの信号点付近以外の部分には、ほとんど存在していないという特徴を持つ。
【００３８】
次に、ＰＲ４に等化された信号を復号する系において、どのようなノイズが発生するとビタビデコーダの復号結果がビットエラーとなるかについて考える。
信号点の振幅を１とすると、ｂｉｔ−ｂｙ−ｂｉｔの振幅検出を行うデコーダでは、時刻ｋにおけるノイズの値ｎ_k が１／２より大きくなったときにエラーとなる。なお正確には、信号値とノイズの極性によってエラーになったりならなかったりするが、ここではそれは無視する。
ＰＲ４用ビタビデコーダでは、概略的に述べると、ある時刻ｋとｌにおけるノイズの大きさの和｜ｎ_k ｜＋｜ｎ_l ｜が１より大きくなった時にエラーとなる可能性が高い。
【００３９】
したがって、ノイズがガウス分布をしているという仮定では、ｎ_k ＝１となる確率はｎ_k ＝１／２となる確率よりも数桁低いため、ビットエラーを起こすノイズのパタンとしては、ノイズの大きさがともに１／２付近の値となっている場合が支配的であると考えられる。
すなわち、ノイズの大きさが１／２付近となった時にビットエラーとなるかならないかの分かれ目となっており、この付近の振幅方向の分解能が重要であるとがわかる。換言すれば、信号存在点の振幅値｛−１，０，１｝付近の分解能や重要ではないと言える。
【００４０】
したがって、信号存在点｛−１，０，１｝付近の量子化ビット幅を粗くとっても、検出特性に影響を与えないようにできる。
たとえば、非線形量子化器によって、＋１６付近の値を全て＋１６に、０付近の値を全て０に、−１６付近の値を全て−１６にそれぞれ変換してビタビデコーダに入力しても、検出特性は劣化しない。
非線形量子化パタンの例として、図７のタイプ１およびタイプ２に示す２種類をそれぞれ用いる場合のビタビデコーダの検出結果の例を図８（Ａ）、（Ｂ）に示す。なお、図７のタイプ１が本実施の形態の非線形量子化器１７で用いた図２に示したパタンである。
【００４１】
ここで、等化器からの信号は６ビットで表現されているとしているので、非線形量子化器に入力される信号ｘは−３２≦ｘ≦３１の値をとる。これに対して、タイプ１では、信号存在点｛−１６，０，１６｝の±２の範囲、および、その外側の値が入力された時にそれぞれ｛−１６，０，１６｝として出力するものであり、タイプ２では、信号存在点｛−１６，０，１６｝の±３の範囲、および、その外側の値が入力された時にそれぞれ｛−１６，０，１６｝として出力するものである。
図８（Ａ）の主要部分を拡大したものを図８（Ｂ）に示す。図８（Ｂ）よりわかるように、タイプ２では非線形量子化を行わない場合に対してビットエラーレートが劣化しているが、タイプ１では全く劣化していない。すなわち、タイプ１のような非線形量子化を行っても検出特性には全く影響を与えないということができる。
【００４２】
ある程度ノイズが少なければ、等化後の信号列はその大部分が＋１６，０，−１６付近のいずれかに存在するので、このような変換をすることによって、ビタビデコーダに入力される信号列はその大部分が＋１６，０，−１６のいずれかになる。
そして、ＰＲ４に等化された信号の振幅基準レベルを１６とすると、ノイズや等化歪みがなければ、信号１の振幅は１６、信号０の振幅は０、信号−１の振幅は−１６となる。実際のハードウェア内部では、２の補数で表現して演算することが多いので、これらを２の補数による６ビットの２進数で表現すると、表１のようになる。
【００４３】
【表１】

【００４４】
一般にロジック回路においては、ノードの値が０または１の間を変化するとより一層電力を消費する。したがって、表１に示したように、＋１６，０，−１６の下位４ビットが０であるビタビデコーダ１８においては、加算器やコンパレータにおける信号の変化が少なくなり、消費電力を低減することができる。
特に、ＣＭＯＳロジック回路においては、ノードが１から０、または０から１へ遷移することによって電力を消費し、ノードのロジックレベルが変化しなければ、全く電力を消費しない特性を持っている。したがって、表１に示したような値が入力され続ける間はビタビデコーダの主要演算部分の中を流れる信号の下位４ビットは全く変化しない。したがって、消費電力の大幅な削減が可能となる。
【００４５】
なお、本発明の回路において新たに必要となる非線形量子化器は、単に入力データを変換して出力するだけのものであるから、その回路規模、消費電力ともに、ビタビデコーダのそれに比べて無視できるほど小さなものである。したがって、本発明のビタビデコーダ全体の回路規模は従来のものと比べてほとんど同じ程度であり、消費電力はビタビデコーダ全体として大幅に削減される。
【００４６】
このように、本実施の形態の磁気ディスク装置においては、ビタビデコーダの検出特性を劣化させることなく、ビタビデコーダの消費電力を大幅に削減することができた。
【００４７】
なお、本発明は本実施の形態に限られるものではなく、種々の改変が可能である。
たとえば、本実施の形態においては、磁気記録チャネルにＰＲ４と８／１０トレリス符号を組み合わせた系を例示して説明したが、その他のＰＲＭＬの形式でも同様の効果を得ることができる。
たとえば、ＥＰＲ４の場合には、｛−２，−１，０，＋１，＋２｝の５値に等化されるので、＋１のレベルを８となるように振幅を調整すると、等化目標は｛−１６，−８，０，＋８，＋１６｝となる。したがって、この場合、非線形量子化器は、ｙ_k が、−３２≦ｙ_k ≦−１５の時は−１６、−９≦ｙ_k ≦−７の時は−８、−２≦ｙ_k ≦＋２の時は０、＋７≦ｙ_k ≦＋９の時は＋８、＋１５≦ｙ_k ≦＋３１の時は＋１６、それ以外の時は入力値をそのまま出力するなどの構成とすればよい。
【００４８】
また、ここでは、８／１０符号を処理する例について述べたが、符号化率がこれと異なる符号を用いる場合には、ローカルパスメモリの処理ビット単位を符号語のビット数と一致させることにより、これと同様の回路を構成する。たとえば、チャネル符号として８／９符号を用いる場合には、ローカルパスメモリの処理ビット単位は９ビットとなる。
【００４９】
また、本実施の形態においては、磁気ディスク装置を例示して本発明を説明したが、本発明の復号化装置は磁気ディスク装置にのみ適用されるものではない。テープ状記録媒体に信号を記録するテープレコーダ、光磁気方式によりディスクより信号を再生する光磁気ディスク装置などに適用してもよい。
また、伝送路を介して伝送される符号化された信号を受信する受信装置に適用してもよい。
また、前述したような記録再生装置に適用する場合に、その記録データには何ら制限されるものではない。デジタルビデオデータ、デジタルオーディオデータを記録してもよいし、通常のデータを記録して計算機装置などのデータレコーダとして用いてもよい。
【００５０】
【発明の効果】
以上説明したように、本発明によれば、パーシャルレスポンスの信号を復号する際に、検出特性を全く劣化させることなく消費電力を大幅に削減した復号化装置を提供することができる。また、検出特性を全く維持した状態で消費電力を大幅に削減することのできる復号化方法を提供することができる。そして、このような低消費電力の復号化装置を搭載することにより、消費電力の少ないデータ再生装置を提供することができる。
【図面の簡単な説明】
【図１】本発明の一実施の形態の磁気ディスク装置の構成を示すブロック図である。
【図２】図１に示した磁気ディスク装置の非線形量子化器におけるデータ変換パタンを示す図である。
【図３】図１に示した磁気ディスク装置のビタビデコーダの構成を示すブロック図である。
【図４】図３に示したビタビデコーダが追跡するトレリスを示す図である。
【図５】図３に示したビタビデコーダのパスメモリの構成を示すブロック図である。
【図６】等化されたデータ列のノイズの分布を示す図である。
【図７】非線形量子化を行う場合のデータ変換パタンを示す図である。
【図８】図７に示した変換を行った場合のデータ検出特性を示す図であり、図８（Ａ）はそのデータ検出特性を示す図、図８（Ｂ）は図８（Ａ）に示した図の中心部の拡大図である。
【図９】従来の磁気ディスク装置の構成を示すブロック図である。
【符号の説明】
１…磁気ディスク装置、１１…チャネル符号化部、１２…記録アンプ、１３…再生アンプ、１４…Ａ／Ｄ変換部、１５…等化器、１６…ＰＬＬ回路、１７…非線形量子化器、１８…ビタビデコーダ、１９…チャネル復号化部、２０…第１の処理回路部、３０…第２の処理回路部、４０…切り替え回路部、５０…合成回路、２１…入力スイッチ、２２…ブランチメトリック演算回路、２３…最尤パスメトリック選択回路、２４…ラッチ、２５…パスメモリ、２５１…ローカルパスメモリ、２５２₁ 〜２５２_-6，２５３₁ 〜２５３_-6，２５４₁ 〜２５４_-6…グローバルパスメモリ、２５５，２５８，２５９…セレクタ、２５６₁ 〜２５６_-6，２５７₁ 〜２５７_-6…ラッチ[0001]
BACKGROUND OF THE INVENTION
The present invention has a decoding apparatus and method, such as a Viterbi decoder, and a decoding apparatus capable of reducing power consumption, and a magnetic recording medium such as a magnetic disk, magnetic tape, and magneto-optical disk. The present invention relates to a data reproducing apparatus capable of appropriately reproducing the signal recorded in the above with low power consumption.
[0002]
[Prior art]
A signal processing method called PRML (Partial Response Maximum Likelihood) combining partial response and maximum likelihood decoding is well known as means for detecting information from a reproduction signal from a magnetic disk or the like.
[0003]
FIG. 9 shows a signal processing circuit using general PRML in a magnetic disk device.
In the magnetic disk device 9 shown in FIG. 9, data input from the hard disk controller is modulated into a channel code by the channel encoder 91 and recorded on the magnetic disk medium 80 via the recording amplifier 92.
The signal reproduced from the magnetic disk medium 80 is amplified by the reproduction amplifier 93, converted into a digital signal by the A / D converter 94, equalized to a signal having the characteristic of PR4 by the equalizer 95, and a Viterbi decoder. 98 is decoded.
[0004]
The Viterbi decoder performs digital arithmetic processing and detects information by estimating the most probable sequence using not only the values of the samples but also the values of the previous and subsequent samples. , A selector and a shift register.
A clock is generated by the PLL circuit 96 based on the signal equalized by the equalizer 95.
The data decoded by the Viterbi decoder 98 is restored to the original signal by the channel decoding unit 99 and output to the hard disk controller.
[0005]
As such PRML types, PR4 and EPR4 are known depending on the type of partial response used, and high detection performance can be obtained by performing more complicated calculations.
There is also a technique called trellis coding PRML (TCPR) in which PRML and a channel code are combined to obtain higher detection performance.
[0006]
[Problems to be solved by the invention]
However, in such PRML, there is a desire to reduce power consumption.
In such PRML, in order to obtain high performance, more complicated calculation is required, and as a result, power consumption of the calculation circuit tends to increase. For example, a Viterbi decoder for EPR4 consumes several times as much power as a Viterbi decoder using PR4. Further, the Viterbi decoder for TCPR consumes more power.
In addition, due to recent advances in semiconductor technology, such signal processing logic circuits are often formed on semiconductor chips. In such cases, there is a demand for reducing power consumption as much as possible. In particular, such a decoding circuit having a relatively large amount of calculation is required to reduce power consumption.
[0007]
Therefore, an object of the present invention is to provide a decoding device capable of reducing power consumption while maintaining performance.
Another object of the present invention is to provide a decoding method capable of reducing power consumption while maintaining performance.
Another object of the present invention is to provide a data reproducing apparatus that has a low power consumption decoding apparatus and can reduce the power consumption of the main body.
[0008]
[Means for Solving the Problems]
In order to solve the above problem, a power consumption is reduced by inserting a non-linear quantizer in the input part of the Viterbi decoder.
[0009]
According to the present invention, an apparatus for decoding a signal based on a partial response, an equalizer for equalizing an input signal to a predetermined signal based on the partial response, and the equalized signal Nonlinear quantization means for nonlinearly quantizing the amplitude value of at least a part of the quantization interval, and decoding means for decoding the original data based on a data sequence of the nonlinear quantized signal Is provided .
[0010]
Preferably, the equalizer includes a number of bits indicating a common value in all equalization target values when the equalization target value of the partial response is expressed in a predetermined binary representation such as 2's complement display. Perform equalization.
Preferably, the nonlinear quantization means has a quantization interval in the vicinity of the PR equalization target value wider than a quantization interval other than in the vicinity of the equalization target value of the partial response. The quantization means performs the quantization on a signal having an amplitude value between equalization target values of different partial responses with a quantization interval narrower than the others.
[0011]
The decoding method of the present invention is a method for decoding a signal based on PR, wherein an input signal is a signal based on a partial response, and an equalization target value of the partial response is set to 2 When expressed in a decimal number, equalization is performed so that many bits indicating a common value are included in all equalization target values, and the amplitude value of the equalized signal is set near the equalization target value of the partial response. Nonlinear quantization is performed so that the quantization interval is wider than the quantization interval other than the partial response equalization target value vicinity, and the original data is obtained by maximum likelihood decoding based on the data sequence of the nonlinear quantized signal. Is decrypted.
[0012]
According to the present invention, a signal detection means for detecting a signal recorded on record medium, the detected signal, when representing the equalization target value of the partial response binary number, all of the equalization target value An equalizer that equalizes a signal based on a partial response that contains many bits indicating a common value in the signal, and an amplitude value of the equalized signal is quantized near the equalization target value of the partial response Based on the nonlinear quantization means for nonlinear quantization so that the interval is wider than the quantization interval other than near the equalization target value of the partial response, and the maximum likelihood decoding method based on the data sequence of the nonlinear quantized signal Provides a data reproducing apparatus having decoding means for decoding the original data.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described with reference to FIGS.
In the present embodiment, a description will be given of a magnetic disk device that records and reproduces a signal on a magnetic disk and includes a Viterbi decoder, which is an example of a decoding device according to the present invention.
[0014]
FIG. 1 is a block diagram showing the configuration of the magnetic disk device.
The magnetic disk apparatus 1 includes a channel encoding unit 11, a recording amplifier 12, a reproduction amplifier 13, an A / D conversion unit 14, an equalizer 15, a PLL circuit 16, a nonlinear quantizer 17, a Viterbi decoder 18, and a channel decoding unit. 19
The magnetic disk device 1 is equipped with a magnetic disk medium 80 which is a recording medium, and signals are recorded and reproduced via a recording head and a reproducing head (not shown).
[0015]
First, the configuration of each part of the magnetic disk device 1 will be described.
The channel encoder 11 converts a recording data signal input from a hard disk controller (not shown) into a signal suitable for magnetic recording on the magnetic disk medium 80 and outputs the signal to the recording amplifier 12.
[0016]
The recording amplifier 12 records the signal input from the channel encoding unit 11 on the magnetic disk medium 80 via a recording head (not shown).
[0017]
The reproduction amplifier 13 amplifies a signal recorded on the magnetic disk medium 80 reproduced by a reproduction head (not shown) and outputs the amplified signal to the A / D conversion unit 14.
[0018]
The A / D conversion unit 14 converts the reproduction signal input from the reproduction amplifier 13 into a digital signal and outputs the digital signal to the equalizer 15.
[0019]
The equalizer 15 equalizes the reproduced digital signal input from the A / D converter 14 into a signal having a partial response class 4 (hereinafter referred to as PR4) characteristic. In the present embodiment, the equalized signal y _k is converted into a value expressed by a 6-bit two's complement, that is, a value of −32 ≦ y _k ≦ 31.
[0020]
The PLL circuit 16 generates a clock from the signal equalized in the equalizer 15, and outputs the clock to the equalizer 15, a control unit (not shown), and each processing unit in the subsequent stage.
[0021]
The nonlinear quantizer 17 performs nonlinear quantization, that is, transforms the signal equalized in the equalizer 15 as shown in FIG. 2 and outputs the result to the Viterbi decoder 18.
FIG. 2 is a diagram showing a conversion pattern in the nonlinear quantizer 17.
As shown in FIG. 2, the nonlinear quantizer 17 outputs −16 when the input signal y _k is −32 ≦ y _k ≦ −14, and the signal y _k is −2 ≦ y _k ≦ + 2. 0 is output, 16 is output when the signal y _k is 14 ≦ y _k ≦ 31, and the input signal y _k is output as it is otherwise.
[0022]
The Viterbi decoder 18 performs maximum likelihood decoding based on the signals sequentially input from the nonlinear quantizer 17 to obtain a code closest to the sequence.
The Viterbi decoder 18 will be described in detail with reference to FIGS.
FIG. 3 is a block diagram showing the configuration of the Viterbi decoder 18.
The Viterbi decoder 18 includes a first processing circuit unit 20, a second processing circuit unit 30, a switching circuit unit 40, and a synthesis circuit 50.
[0023]
The first processing circuit unit 20 and the second processing circuit unit 30 are circuits for processing an even bit sequence and an odd bit sequence of input bit data, respectively, and have exactly the same internal configuration. . Accordingly, only the first processing circuit unit 20 will be described in detail here and the operation will be described.
The first processing circuit unit 20 includes an input switch 21, a branch metric calculation circuit 22, a maximum likelihood path metric selection circuit 23, a latch 24, and a path memory 25.
[0024]
Further, the trellis tracked by the Viterbi decoder for each series of the first processing circuit unit 20 and the second processing circuit unit 30 is as shown in FIG. That is, there are six states inside, and processing is performed by combining two consecutive sample values.
[0025]
In such a Viterbi decoder 18, signals sequentially input from the nonlinear quantizer 17 are converted into switching signals from the switching circuit unit 40 by the input switches 21 of the first processing circuit unit 20 and the second processing circuit unit 30. Based on this, every other bit is deinterleaved and fetched into the first processing circuit unit 20 that processes even-numbered sequences and the second processing circuit unit 30 that processes odd-numbered sequences.
Sequentially captured samples in the first processing circuit section 20 is input to branch metric calculation circuit 22, based on equation (1) to (7), the value bm _-10 to Bm ₁₀ is calculated.
[0026]
[Expression 1]

[0027]
In equations (1) to (7), the values of two consecutive samples selected by the input switch 21 are z ₁ and z ₂ , and the amplitude reference level is R.
[0028]
Next, the maximum likelihood path metric selection circuit 23 selects the maximum likelihood branch according to the rules shown in the equations (8) to (13), and the path metric is latched by the latch 24.
[0029]
[Expression 2]

[0030]
The result of selecting the maximum likelihood branch is sent to the path memory 25, and the path memory 25 performs processing for narrowing the surviving path to one from the information.
[0031]
The path determined as the surviving path is output as detection data, and is combined with the output signal from the second processing circuit unit 30 by the combining circuit 50 based on the switching signal from the switching circuit unit 40, and is an even / odd series. The combined data is output from the Viterbi decoder 18.
[0032]
FIG. 5 shows a detailed block diagram of the path memory portion.
The path memory 25 is a local path memory 251 having a length of 10 bits equal to the codeword length, and a global path memory 252 _{1 to} 252 _-6 , 253 _{1 to} 253 _-6 , 254 ₁ that is similarly shifted in units of 10 samples. having ～254 _-6.
The local path memory 251 is constituted by a parallel load / serial shift register, determines the surviving path of the first 10 samples, and outputs it in units of 10 bits for each state. The surviving path is shifted by the global bus memory, and finally the maximum likelihood path is selected and output by the selector 255.
Since the number of states is 6, the state 10 samples before can be expressed by 3-bit data, which is shifted by latches 256 _{1 to} 256 _-6 and latches 257 _{1 to} 257 _-6 .
Since the output of the selector 259 represents the state 20 samples before and the output of the selector 258 represents the state 30 samples before, the output of the selector 255 represents the surviving path 30 samples before and is output as decoded data.
[0033]
The channel decoding unit 19 converts the signal decoded by the Viterbi decoder 18 into a basic digital signal and outputs it to the hard disk controller.
[0034]
Next, the operation of the magnetic disk device 1 will be described together.
In the magnetic disk device 1, data to be recorded is input from a hard disk controller (not shown), modulated to a channel code by a channel encoding unit 11, and recorded on a magnetic disk medium 80 from a recording head (not shown) via a recording amplifier 12. To be recorded.
[0035]
Then, a signal reproduced from the magnetic disk medium 80 by a reproducing head (not shown) is amplified by the reproducing amplifier 13 and converted into a digital signal by the A / D converter 14, and converted into a signal having the characteristic of PR4 by the equalizer 15. Equalized. At this time, the equalized signal y _k is expressed by a 6-bit two's complement and takes a value of −32 ≦ y _k ≦ + 31.
A clock is generated by the PLL circuit 16 based on the equalized signal.
The equalized signal is rounded to a discrete value by the nonlinear quantizer 17, then decoded by the Viterbi decoder 18, restored to the original signal by the channel decoder 19, and passed through a hard disk controller (not shown). Is output.
[0036]
Next, detection is performed by such a magnetic disk device 1, that is, by providing a nonlinear quantizer 17 before decoding by the Viterbi decoder 18 and performing nonlinear quantization based on the pattern as shown in FIG. The fact that the characteristics are not deteriorated and that the power consumption can be reduced by this will be described with reference to FIGS.
In a system using PR4 equalization, the signal existence point is a ternary value of {-1, 0, +1}.
When the sample value equalized to PR4 is expressed with a 6-bit width and the amplitude is adjusted so that the signal amplification of +1 becomes +16, the signal existence point can be expressed as {−16, 0, +16}.
Actually, the sample values are distributed so as to have a Gaussian distribution around the signal existing point due to the influence of equalization error and noise.
[0037]
FIG. 6 shows a distribution of sample rows obtained by PR4 equalization of the reproduction signal from the magnetic recording system. In FIG. 6, the ● mark is an experimental value, and the broken line is a curve showing a Gaussian distribution. As shown in FIG. 6, as described above, every level of {−16, 0, +16} has a substantially Gaussian distribution.
Thus, most of the sample train in which the reproduction signal from the magnetic recording system is equalized to PR4 is unevenly distributed in the vicinity of the signal point. Has a feature that almost does not exist.
[0038]
Next, what kind of noise occurs in the system for decoding the signal equalized to PR4 will be considered as a bit error in the decoding result of the Viterbi decoder.
If the amplitude of a signal point is 1, a decoder that detects a bit-by-bit amplitude will generate an error when the noise value n _{k at} time k is greater than ½. To be precise, an error does not occur depending on the signal value and the polarity of noise, but this is ignored here.
In the PR4 Viterbi decoder, generally speaking, there is a high possibility of an error when the sum of noise magnitudes | n _k | + | n _l |
[0039]
Thus, the assumption that noise has a Gaussian distribution, since the probability of n _k = 1 is several orders of magnitude lower than the probability of n _k = 1/2, as the pattern of the noise causing bit errors, noise It is considered that the case where the magnitudes are both about ½ is dominant.
That is, it is a part of whether or not a bit error may occur when the magnitude of noise is about ½, and it can be seen that the resolution in the amplitude direction in the vicinity is important. In other words, it can be said that the resolution near the amplitude value {−1, 0, 1} of the signal existence point is not important.
[0040]
Therefore, even if the quantization bit width in the vicinity of the signal existence point {-1, 0, 1} is coarse, the detection characteristics can be prevented from being affected.
For example, even if a non-linear quantizer converts all values near +16 to +16, all values near 0 to 0, all values near -16 to -16, and inputs them to the Viterbi decoder, the detection characteristics Does not deteriorate.
8A and 8B show examples of detection results of the Viterbi decoder when using two types shown in type 1 and type 2 in FIG. 7 as examples of nonlinear quantization patterns. 7 is the pattern shown in FIG. 2 used in the nonlinear quantizer 17 of the present embodiment.
[0041]
Here, since the signal from the equalizer is expressed by 6 bits, the signal x input to the nonlinear quantizer takes a value of −32 ≦ x ≦ 31. On the other hand, in type 1, when a range of ± 2 of the signal existence point {−16, 0, 16} and a value outside thereof are input, they are output as {−16, 0, 16}, respectively. In type 2, when a range of ± 3 of the signal existence point {−16, 0, 16} and a value outside thereof are input, they are output as {−16, 0, 16}, respectively. .
FIG. 8B shows an enlarged view of the main part of FIG. As can be seen from FIG. 8B, the bit error rate is degraded in Type 2 as compared to the case where nonlinear quantization is not performed, but in Type 1, it is not degraded at all. That is, it can be said that even if nonlinear quantization such as type 1 is performed, the detection characteristics are not affected at all.
[0042]
The less any size enough that the signal sequence after equalization that most of + 16,0, since present either in the vicinity of -16, by such conversion, is input to the Viterbi decoder Most of the signal sequence is +16, 0, or -16.
If the amplitude reference level of the signal equalized to PR4 is 16, if there is no noise or equalization distortion, the amplitude of signal 1 is 16, the amplitude of signal 0 is 0, and the amplitude of signal-1 is -16. Become. In actual hardware, there are many cases where the calculation is performed by expressing with two's complement, and when these are expressed by 6-bit binary numbers with two's complement, Table 1 is obtained.
[0043]
[Table 1]

[0044]
In general, in a logic circuit, when the value of a node changes between 0 and 1, more power is consumed. Therefore, as shown in Table 1, in the Viterbi decoder 18 in which the lower 4 bits of +16, 0, and −16 are 0, the signal change in the adder and the comparator is reduced, and the power consumption can be reduced. .
In particular, the CMOS logic circuit, the node will consume power by transitioning from 1 0 or 1 to 0, unless LOGIS click level of the node is changed, to possess characteristics quite no power consumption . Therefore, while the values as shown in Table 1 are continuously input, the lower 4 bits of the signal flowing in the main arithmetic part of the Viterbi decoder do not change at all. Therefore, power consumption can be greatly reduced.
[0045]
Since the nonlinear quantizer newly required in the circuit of the present invention simply converts the input data and outputs it, the circuit scale and power consumption can be ignored compared to those of the Viterbi decoder. It is so small. Therefore, the circuit scale of the entire Viterbi decoder of the present invention is almost the same as that of the conventional Viterbi decoder, and the power consumption is greatly reduced as a whole Viterbi decoder.
[0046]
Thus, in the magnetic disk device of this embodiment, the power consumption of the Viterbi decoder can be greatly reduced without degrading the detection characteristics of the Viterbi decoder.
[0047]
The present invention is not limited to the present embodiment, and various modifications can be made.
For example, in the present embodiment, a system in which PR4 and an 8/10 trellis code are combined with a magnetic recording channel has been described as an example. However, similar effects can be obtained with other PRML formats.
For example, in the case of EPR4, since it is equalized to five values of {-2, -1, 0, +1, +2}, if the amplitude is adjusted so that the level of +1 becomes 8, the equalization target is { −16, −8, 0, +8, +16}. Therefore, in this case, the nonlinear quantizer is -16 when y _k is −32 ≦ y _k ≦ −15, -8 when −9 ≦ y _k ≦ −7, and −2 ≦ y _k ≦ + 2. For example, 0 may be used, +8 when + 7 ≦ y _k ≦ + 9, +16 when + 15 ≦ y _k ≦ + 31, and the input value may be output as it is otherwise.
[0048]
Although an example of processing an 8/10 code has been described here, when a code with a different coding rate is used, the processing bit unit of the local path memory is matched with the number of bits of the code word. A circuit similar to this is constructed. For example, when an 8/9 code is used as a channel code, the processing bit unit of the local path memory is 9 bits.
[0049]
In the present embodiment, the present invention has been described by exemplifying a magnetic disk device. However, the decoding device of the present invention is not applied only to the magnetic disk device. You may apply to the tape recorder which records a signal on a tape-shaped recording medium, the magneto-optical disk apparatus etc. which reproduce | regenerate a signal from a disk by a magneto optical system.
Moreover, you may apply to the receiver which receives the encoded signal transmitted via a transmission line.
Further, when applied to the recording / reproducing apparatus as described above, the recording data is not limited at all. Digital video data and digital audio data may be recorded, or ordinary data may be recorded and used as a data recorder such as a computer apparatus.
[0050]
【The invention's effect】
As described above, according to the present invention, when decoding a partial response signal, it is possible to provide a decoding apparatus that significantly reduces power consumption without causing any deterioration in detection characteristics. In addition, it is possible to provide a decoding method that can significantly reduce power consumption while maintaining detection characteristics. By mounting such a low power consumption decoding device, a data reproducing device with low power consumption can be provided.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a magnetic disk device according to an embodiment of the present invention.
FIG. 2 is a diagram showing a data conversion pattern in the nonlinear quantizer of the magnetic disk device shown in FIG. 1;
3 is a block diagram showing a configuration of a Viterbi decoder of the magnetic disk device shown in FIG. 1. FIG.
4 is a diagram showing a trellis tracked by the Viterbi decoder shown in FIG. 3; FIG.
5 is a block diagram showing a configuration of a path memory of the Viterbi decoder shown in FIG. 3;
FIG. 6 is a diagram illustrating a noise distribution of an equalized data string.
FIG. 7 is a diagram showing a data conversion pattern when nonlinear quantization is performed.
8 is a diagram showing data detection characteristics when the conversion shown in FIG. 7 is performed, FIG. 8 (A) is a diagram showing the data detection characteristics, and FIG. 8 (B) is a diagram in FIG. 8 (A). It is an enlarged view of the center part of the figure shown.
FIG. 9 is a block diagram showing a configuration of a conventional magnetic disk device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Magnetic disk apparatus, 11 ... Channel encoding part, 12 ... Recording amplifier, 13 ... Reproduction amplifier, 14 ... A / D conversion part, 15 ... Equalizer, 16 ... PLL circuit, 17 ... Nonlinear quantizer, 18 DESCRIPTION OF SYMBOLS ... Viterbi decoder, 19 ... Channel decoding part, 20 ... 1st processing circuit part, 30 ... 2nd processing circuit part, 40 ... Switching circuit part, 50 ... Synthesis circuit, 21 ... Input switch, 22 ... Branch metric calculation Circuit: 23 ... Maximum likelihood path metric selection circuit, 24 ... Latch, 25 ... Path memory, 251 ... Local path memory, 252 _{1 to} 252 _-6 , 253 _{1 to} 253 _-6 , 254 _{1 to} 254 _-6 ... Global path memory , 255, 258, 259... Selector, 256 _{1 to} 256 _-6 , 257 _{1 to} 257 _-6 .

Claims (9)

An apparatus for decoding a signal based on a partial response,
An equalizer that equalizes an input signal to a predetermined signal based on a partial response; and a nonlinear that quantizes the amplitude value of the equalized signal so that at least some of the quantization intervals are different Quantization means;
A decoding apparatus comprising: decoding means for decoding original data based on a data sequence of the nonlinear quantized signal. The equalizer performs the equalization so that many equality target values are included in all equalization target values when a partial response equalization target value is expressed in a predetermined binary representation.
The decoding device according to claim 1. The nonlinear quantization means performs the quantization so that a quantization interval near the equalization target value of the partial response is wider than a quantization interval other than near the equalization target value of the partial response.
The decoding device according to claim 2. The nonlinear quantization means performs the quantization with a quantization interval narrower than others for a signal having an amplitude value between equalization target values of different partial responses.
The decoding device according to claim 3. The decoding means decodes the data by maximum likelihood decoding;
The decoding device according to claim 4. The decoding means decodes the data by a Viterbi decoding method;
The decoding device according to claim 5. The decoding means is constituted by a CMOS circuit.
The decoding device according to claim 5. A method of decoding a signal based on a partial response,
When the input signal is a signal based on a partial response, and the equalization target value of the partial response is expressed in binary, many bits indicating a common value are included in all equalization target values Equalization,
Non-linear quantization of the amplitude value of the equalized signal so that the quantization interval near the equalization target value of the partial response is wider than the quantization interval other than near the equalization target value of the partial response,
Based on the data sequence of the nonlinear quantized signal, the original data is decoded by a maximum likelihood decoding method.
Decryption method. Signal detecting means for detecting a signal recorded on record medium,
The detected signal is equalized to a signal based on a partial response so that when the equalization target value of the partial response is expressed in binary, all the equalization target values include many bits indicating a common value. An equalizer to perform,
Non-linear quantization that non-linearly quantizes the amplitude value of the equalized signal so that the quantization interval near the equalization target value of the partial response is wider than the quantization interval other than near the equalization target value of the partial response And
A data reproducing apparatus comprising: decoding means for decoding original data by a maximum likelihood decoding method based on a data sequence of the nonlinear quantized signal.

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