JPH01307294A - Multilayer printed board - Google Patents

Multilayer printed board

Info

Publication number
JPH01307294A
JPH01307294A JP13791988A JP13791988A JPH01307294A JP H01307294 A JPH01307294 A JP H01307294A JP 13791988 A JP13791988 A JP 13791988A JP 13791988 A JP13791988 A JP 13791988A JP H01307294 A JPH01307294 A JP H01307294A
Authority
JP
Japan
Prior art keywords
layer
printed circuit
circuit board
foamed
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13791988A
Other languages
Japanese (ja)
Inventor
Shigeru Tomizawa
富沢 茂
Keiji Kurosawa
黒沢 啓治
Takao Kobayashi
隆雄 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13791988A priority Critical patent/JPH01307294A/en
Publication of JPH01307294A publication Critical patent/JPH01307294A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To transmit a signal at high speed by a low dielectric constant, and to use a base substrate consisting of an organic material such as a glass epoxy resin by composing an insulating layer of an adhesive layer made up of a sheet-shaped foamed fluoroplastic resin layer coated or impregnated with a thermosetting resin. CONSTITUTION:An adhesive layer (a prepreg layer) in which a through-hole 34 is bored and worked to a material, in which foamed fluoro-plastics 33 are coated or impregnated with a thermosetting resin 32 under the state of a stage B, by using punching working is pressed and laminated. Pressure bonding is conducted by curing under pressure at the curing temperature (170-200 deg.C) of a conventional thermosetting resin by the pressure laminating of the adhesive layer. Consequently, a substrate consisting of an organic material such as a glass epoxy resin can be employed besides a ceramic substrate as a substrate material, and the degree of freedom of the selection of the substrate is improved. Since the foamed floroplastics are used, the bubbles of air are contained in the foamed fluoroplastics, and the dielectric constant of the foamed fluoroplastics displays a value between the value of 2.1 of fluoroplastics and the value of 1 of the dielectric constant of air, and a signal can be transmitted at high speed.

Description

【発明の詳細な説明】 〔目 次〕 概要・・・・・・・・・・・・・・・・・・・・・・・
・・・・・・・・・・・・・・・・・・・3頁産業上の
利用分野・・・・・・・・・・・・・・・・・・・・・
・・・・・・・・・3頁従来の技術・・・・・・・・・
・・・・・・・・・・・・・・・・・・・・・・・・・
・・・・・4頁発明が解決しようとする課題・・・・・
・・・・・・・・・・6頁課題を解決するための手段・
・・・・・・・・・・・・・・・・・8頁作用・・・・
・・・・・・・・・・・・・・・・・・・・・・・・・
・・・・・・・・・・・・・・・・・・・8頁実施例・
・・・・・・・・・・・・・・・・・・・・・・・・・
・・・・・・・・・・・・・・・・・・・10頁第1実
施例の構造と製造方法・・・・・・・・・10−12頁
第2実施例の構造と製造方法・・・・・・・・・12〜
15頁第3実施例の構造と製造方法・・・・・・・・・
15〜17頁第4実施例の構造と製造方法・・・・・・
・・・17〜19頁第5実施例の構造と製造方法・・・
・・・・・・19〜21頁第6実施例の構造と製造方法
・・・・・・・・・・・・・・・21頁第7実施例の構
造と製造方法・・・・・・・・・21〜23頁発明の効
果・・・・・・・・・・・・・・・・・・・・・・・・
・・・・・・・・・・・・・・・23頁〔概 要〕 多層プリント基板に関し、 低誘電率で信号の高速伝送を可能にし、ガラスエポキシ
樹脂のような有機材料よりなるベース基板が使用でき、
低弾性率で応力の発生が少なく、スパッタ法を用いずに
、無電解銅メツキ法等の化学メツキ法で導電体層が形成
できる多層プリント基キ反を目的とし、 所定のパターンの導体層と絶縁層とを多層に有する多層
プリント基板に於いて、 前記絶縁層が熱硬化性樹脂を塗布、或いは含浸させたシ
ート状の発泡弗素樹脂層よりなる接着層で構成する。
[Detailed description of the invention] [Table of contents] Overview
・・・・・・・・・・・・・・・・・・・・・3 pages Industrial application fields・・・・・・・・・・・・・・・・・・・・・
・・・・・・・・・Page 3 Conventional technology・・・・・・・・・
・・・・・・・・・・・・・・・・・・・・・・・・
...Page 4 Problems to be solved by the invention...
・・・・・・・・・Means to solve the problem on page 6・
・・・・・・・・・・・・・・・・・・Page 8 Effects・・・・
・・・・・・・・・・・・・・・・・・・・・・・・
・・・・・・・・・・・・・・・・・・8 pages Example・
・・・・・・・・・・・・・・・・・・・・・・・・
・・・・・・・・・・・・・・・・・・Page 10 Structure and manufacturing method of the first embodiment ・・・・・・Pages 10-12 Structure and structure of the second embodiment Manufacturing method...12~
Page 15 Structure and manufacturing method of the third embodiment...
Pages 15-17 Structure and manufacturing method of the fourth embodiment...
...Pages 17-19 Structure and manufacturing method of the fifth embodiment...
・・・・・・Pages 19-21 Structure and manufacturing method of the 6th embodiment ・・・・・・・・・・・・・・・Page 21 Structure and manufacturing method of the 7th embodiment・・・・・・Pages 21-23 Effects of the invention・・・・・・・・・・・・・・・・・・・・・・・・・・・
・・・・・・・・・・・・・・・Page 23 [Summary] Regarding multilayer printed circuit boards, base substrates made of organic materials such as glass epoxy resin that enable high-speed signal transmission with a low dielectric constant. can be used,
The purpose is to create a multilayer printed substrate that has a low elastic modulus, generates little stress, and can form a conductive layer using a chemical plating method such as electroless copper plating without using a sputtering method. In a multilayer printed circuit board having multiple insulating layers, the insulating layer is composed of an adhesive layer made of a sheet-like foamed fluororesin layer coated with or impregnated with a thermosetting resin.

[産業上の利用分野〕 本発明は多層プリント基板に関する。[Industrial application field] The present invention relates to a multilayer printed circuit board.

高密度実装を可能にするために、セラミックよりなる絶
縁性基板上に、所定のパターンに形成された導体層パタ
ーンを有する熱硬化性のポリイミド層等の絶縁層を加圧
積層し、これらの導体層パターン間をスルーホールで接
続した多層プリント基板が用いられている。
In order to enable high-density mounting, an insulating layer such as a thermosetting polyimide layer having a conductor layer pattern formed in a predetermined pattern is laminated under pressure on an insulating substrate made of ceramic, and these conductors are laminated under pressure. A multilayer printed circuit board is used in which layer patterns are connected through through holes.

〔従来の技術〕[Conventional technology]

従来の多層プリント基板の構造を第9図に示す。 The structure of a conventional multilayer printed circuit board is shown in FIG.

図示するように、従来の第1の多層プリント基板の例と
してセラミックよりなる絶縁性基板l上に、蒸着、或い
はスパッタ法とレジストパターンをマスクとするエツチ
ング法により金属パターン2が形成されている。更に該
金属パターン2上に感光性のポリイミド層3が塗布され
、露光、現像により該ポリイミド層3に所定パターンの
スルーホール4が形成され、該スルーホール内に導体層
5をスパッタ後、更に該ポリイミド層3上に前記した金
属層をスパッタ、或いは蒸着により形成後、この金属層
を所定の第2層の金属パターン2に形成している。更に
これらの金属パターンを複数層積層してビルドアップ型
構造の多層プリント基板が形成される。
As shown in the figure, a metal pattern 2 is formed on an insulating substrate l made of ceramic as an example of a first conventional multilayer printed circuit board by vapor deposition or sputtering and an etching method using a resist pattern as a mask. Furthermore, a photosensitive polyimide layer 3 is coated on the metal pattern 2, and a predetermined pattern of through holes 4 are formed in the polyimide layer 3 by exposure and development. After forming the metal layer described above on the polyimide layer 3 by sputtering or vapor deposition, this metal layer is formed into a predetermined second layer metal pattern 2. Furthermore, a multilayer printed circuit board having a build-up type structure is formed by laminating a plurality of layers of these metal patterns.

また従来の第2の多層プリント基板の例とじて高速コン
ピュータに用いられる多層プリント基板として第10図
に示すように、ガラス布と弗素樹脂(ポリテトラフルオ
ロエチレン: PTFE樹脂)から成る基材11の両面
に信号配線パターン12を形成し、電源配線パターン1
3を形成したガラス布と弗素樹脂から成る基材14との
間に、接着層として前記PTFEより低融点の弗素樹脂
(フルオリネイテッドエチレンプロピレン樹脂: FE
P樹脂)をガラス布に含浸させた接着層(プリプレグ)
15を積層して形成されている。
As shown in FIG. 10, a second conventional multilayer printed circuit board for use in high-speed computers has a base material 11 made of glass cloth and fluororesin (polytetrafluoroethylene: PTFE resin). A signal wiring pattern 12 is formed on both sides, and a power wiring pattern 1 is formed on both sides.
A fluororesin (fluorinated ethylene propylene resin: FE) having a lower melting point than the PTFE is used as an adhesive layer between the glass cloth on which 3 is formed and the base material 14 made of fluororesin.
Adhesive layer (prepreg) made by impregnating glass cloth with P resin)
15 are laminated.

更に従来の第3の多層プリント基板の例として大電流を
消費する電子回路を搭載するプリント基板として大電流
を給電でき、熱放散の良い銅板を内蔵した金属コア内蔵
型プリント基板が有る。この構造は第11図に示すよう
に孔加工を施し、熱アルカリ性溶液を用いて表面を酸化
することで黒化処理を行い樹脂層との接着を強固にした
分厚い金属コアとなる銅板21と銅箔の22の間に、エ
ポキシ樹脂を含浸させたガラス布よりなる接着層(プリ
プレグ層)23を加圧加熱成形した後、スルーホール2
4を開口し、該スルーホール内に無電解消メツキおよび
電解銅メツキを形成している。
Further, as an example of the third conventional multilayer printed circuit board, there is a printed circuit board with a built-in metal core that can supply a large current and has a built-in copper plate with good heat dissipation as a printed circuit board on which an electronic circuit that consumes a large current is mounted. As shown in Figure 11, this structure consists of a copper plate 21 that forms a thick metal core, which is made with holes and whose surface is blackened by oxidizing it with a hot alkaline solution to strengthen the adhesion with the resin layer. After pressing and heating an adhesive layer (prepreg layer) 23 made of glass cloth impregnated with epoxy resin between the foils 22, the through holes 2 are formed.
4 is opened, and electroless plating and electrolytic copper plating are formed in the through hole.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

然し、このような第1の例のビルドアップ型構造の多層
プリント基板は、金属パターン上に形成されるポリイミ
ド層が平坦な状態に形成されず、金属パターンの箇所で
段差を有するようになり、形成される多層構造のプリン
ト基板の表面が平坦にならない問題がある。更にポリイ
ミド樹脂の硬化温度が400℃前後の高温となり、ガラ
スエポキシ樹脂よりなる有機材料の基板が、その硬化温
度で変形する問題がある。またポリイミド樹脂の誘電率
が3.5以下とならず、信号の高速伝送の妨げとなる。
However, in the multilayer printed circuit board with the build-up type structure of the first example, the polyimide layer formed on the metal pattern is not formed in a flat state, but has a step difference at the location of the metal pattern. There is a problem that the surface of the printed circuit board having a multilayer structure that is formed is not flat. Furthermore, the curing temperature of the polyimide resin is high, around 400° C., and there is a problem that the organic material substrate made of glass epoxy resin is deformed at the curing temperature. Furthermore, the dielectric constant of the polyimide resin is not lower than 3.5, which impedes high-speed signal transmission.

更に基板にセラミック基板を用いると、前記したポリイ
ミド樹脂と熱膨張係数が異なるため、ポリイミド樹脂に
クランクが入る問題がある。
Furthermore, if a ceramic substrate is used as the substrate, there is a problem that the crank may enter the polyimide resin because the coefficient of thermal expansion is different from that of the polyimide resin described above.

またポリイミド樹脂層上の導体層は、スパッタ法で形成
しないと、樹脂層に対して密着性が悪く、無電解メツキ
のような化学メツキが使用できないため、工程が煩雑に
なる。
Further, unless the conductor layer on the polyimide resin layer is formed by sputtering, it will have poor adhesion to the resin layer, and chemical plating such as electroless plating cannot be used, making the process complicated.

また第2の多層プリント基板の例として高速コンピュー
タに用いられる多層プリント基板はガラス布と弗素樹脂
(ポリテトラフルオロエチレン:PTFE樹脂)からな
る基材11の両面に、該基材を構成するPTFE樹脂よ
り更に低融点のPEP樹脂、或いはPPA樹脂(パーフ
ルオルアルコキシ樹脂)を用いているが、この両者の樹
脂はいずれも融点が高く、熱可塑性で樹脂が硬化する成
形温度が300°C以上あり、基材に最も融点の高いP
TFH樹脂を用いているにも係わらず、熱可塑性のため
、加圧加熱成形時に基材が軟化し始め、基材に設けた中
間層の内層回路の位置が変動する問題がある。
Further, as an example of a second multilayer printed circuit board, a multilayer printed circuit board used in a high-speed computer has a base material 11 made of glass cloth and a fluororesin (polytetrafluoroethylene: PTFE resin), and a PTFE resin constituting the base material is coated on both sides of the base material 11. PEP resin or PPA resin (perfluoroalkoxy resin), which has an even lower melting point, is used, but both resins have high melting points and are thermoplastic and have a molding temperature of 300°C or higher at which the resin hardens. , P with the highest melting point in the base material
Despite the use of TFH resin, due to its thermoplasticity, the base material begins to soften during pressure and heat molding, causing a problem in which the position of the inner layer circuit of the intermediate layer provided on the base material fluctuates.

更に第3の多層プリント基板の例として金属コアを内蔵
したプリント基板を形成する際、分厚い金属コアとなる
銅板にスルーホールを開口する際、銅板とエポキシ樹脂
をガラス布に含浸させたプリプレグ層(接着層)との境
界面でこのプリプレグ層の弾性率が高いために銅板より
剥離する欠点がある。
Furthermore, when forming a printed circuit board with a built-in metal core as an example of the third multilayer printed circuit board, when opening a through hole in a copper plate that will become a thick metal core, a prepreg layer (made by impregnating a copper plate and an epoxy resin in a glass cloth) is used. This prepreg layer has a high elastic modulus at the interface with the adhesive layer (adhesive layer), so it has the disadvantage of peeling off from the copper plate.

本発明は上記した問題点を解決し、低誘電率、低弾性率
で基板にを機、或いは無機材料の基板が用いられ、かつ
化学メツキが容易にできる多層プリント基板の提供を目
的とする。
The present invention solves the above-mentioned problems, and aims to provide a multilayer printed circuit board in which a substrate is made of an organic or inorganic material with a low dielectric constant and a low elastic modulus, and which can be easily chemically plated.

〔課題を解決するための手段〕[Means to solve the problem]

」二記目的を達成する本発明の多層プリント基板は、第
1図の原理図に示すように、所定のパターンの導体層1
00と絶縁N200とを多層に有する多層プリント基板
に於いて、 前記絶縁層200が、熱硬化性樹脂層を塗布した、或い
は熱硬化性樹脂を含浸したシート状の発泡弗素樹脂層よ
りなる接着層であることを特徴としている。
The multilayer printed circuit board of the present invention, which achieves the second object, has a conductor layer 1 of a predetermined pattern, as shown in the principle diagram of FIG.
In a multilayer printed circuit board having multiple layers of 00 and insulating N200, the insulating layer 200 is an adhesive layer made of a sheet-like foamed fluororesin layer coated with a thermosetting resin layer or impregnated with a thermosetting resin. It is characterized by being

〔作 用〕[For production]

本発明の多層プリント基板は、発泡弗素樹脂にBステー
ジ状態の熱硬化性樹脂を塗布、或いは含浸した材料にパ
ンチング加工を用いてスルーホールを孔開は加工した接
着層(プリプレグ層)を加圧積層する。この発泡弗素樹
脂は商品名をボアテックスと称し、ジャパンボアテック
ス社製で、PTFEを溶媒に分散させた後、微粉末を取
り出し加圧成形後、延伸した発泡体で内部に多数の気泡
を有する材料である。
The multilayer printed circuit board of the present invention is produced by applying pressure to an adhesive layer (prepreg layer) in which through-holes are formed using a punching process in a material in which a thermosetting resin in a B-stage state is coated or impregnated on foamed fluororesin. Laminate. The product name of this foamed fluororesin is Boretex, and it is manufactured by Japan Boretex Co., Ltd. After dispersing PTFE in a solvent, the fine powder is taken out, pressure molded, and then stretched into a foam that has many air bubbles inside. It is the material.

この接着層の加圧積層によって加圧接着が従来の熱硬化
型樹脂の硬化温度(170〜200℃)で加圧硬化でき
るため、基板材料としてセラミック基板以外にガラスエ
ポキシ樹脂のようなを機材料の基板を用いることができ
、基板の選択の自由度が向上する。
By laminating the adhesive layer under pressure, the adhesive can be cured under pressure at the curing temperature of conventional thermosetting resins (170 to 200°C). substrates can be used, increasing the degree of freedom in selecting substrates.

また発泡弗素樹脂を用いることで、樹脂内に空気の気泡
が含有され、該発泡樹脂の誘電率が弗素樹脂の2.1の
値と、気泡の空気の誘電率1の値の間の値を呈するよう
になり、信号の高速伝送が可能となる。
Furthermore, by using a foamed fluororesin, air bubbles are contained within the resin, and the dielectric constant of the foamed resin is between the value of 2.1 for the fluororesin and the dielectric constant of 1 for the air in the bubbles. This makes it possible to transmit signals at high speed.

また発泡弗素樹脂層の表面は気泡が含まれているため、
粗面状を呈しており、その上にコートされる熱硬化型樹
脂層との密着度が向上する。
In addition, since the surface of the foamed fluororesin layer contains air bubbles,
It has a rough surface, which improves the degree of adhesion with the thermosetting resin layer coated thereon.

また弾性率が低下するため、絶縁層の応力の発生が少な
くなり、ベース基板が有機、無機の何れにも通用できる
。また応力の発生が少ないため、部品が直接実装できる
。また熱硬化性樹脂で導体層パターンを固定できるので
、回路形成が容易となる。
Furthermore, since the elastic modulus is lowered, stress generation in the insulating layer is reduced, and the base substrate can be used for both organic and inorganic materials. Additionally, since little stress is generated, parts can be directly mounted. Further, since the conductor layer pattern can be fixed with a thermosetting resin, circuit formation is facilitated.

また樹脂コート面を加熱、加圧接着する際、基板側の面
と逆方向の面は、粗化フィルムの面を転写させることが
できるので、化学的に銅メツキ層を容易に形成でき、ス
パッタ法によらずとも容易に銅メツキ層が形成できる。
In addition, when bonding the resin coated surface under heat and pressure, the surface opposite to the substrate side can transfer the surface of the roughened film, making it easy to form a copper plating layer chemically and using sputtering. A copper plating layer can be easily formed without using any method.

〔実施例〕〔Example〕

以下、図面を用いながら本発明の実施例につき詳細に説
明する。
Embodiments of the present invention will be described in detail below with reference to the drawings.

前記したビルドアップ型多層プリント基板の構造に付い
て説明する。
The structure of the build-up multilayer printed circuit board described above will be explained.

第2図(i)は本発明の多層プリント基板の第1実施例
で、ビルドアップ型多層プリントの基板の片面ビルドア
ップ型構造の断面図である。
FIG. 2(i) shows a first embodiment of the multilayer printed circuit board of the present invention, and is a sectional view of a single-sided built-up type structure of a built-up type multilayer printed circuit board.

図示するように銅板等よりなる支持vi、31上に、両
面にポリイミド樹脂のような熱硬化性樹脂32カ塗布形
成されたシート状の第1層の発泡弗素樹脂33が積層さ
れ、該樹脂33にはスルーボール34が形成され、その
内部に電解銅メツキ層36が形成されている。
As shown in the figure, a first layer of foamed fluororesin 33 coated with a thermosetting resin 32 such as polyimide resin on both surfaces is laminated on a support vi, 31 made of a copper plate or the like. A through ball 34 is formed in the through ball 34, and an electrolytic copper plating layer 36 is formed inside the through ball 34.

更にこのスルーホール34上と発泡弗素樹脂層33上に
は所定パターンの無電解銅メツキ層35と電解銅メツキ
層36よりなる電源回路パターン37が形成され、その
上には両面に熱硬化性樹脂32を塗布した第2層の発泡
弗素樹脂層38が形成され、スルーホール34内の電解
銅メツキ層36を通じて無電解銅メツキ層35と電解銅
メツキ層36よりなる信号回路パターン39が形成され
ている。更に支持板31の金属板をエツチング除去する
ことで片面ビルドアップ型のプリン)5板が形成できる
Furthermore, a power circuit pattern 37 consisting of a predetermined pattern of an electroless copper plating layer 35 and an electrolytic copper plating layer 36 is formed on the through hole 34 and the foamed fluororesin layer 33, and a thermosetting resin is coated on both sides of the power circuit pattern 37. A second foamed fluororesin layer 38 coated with 32 is formed, and a signal circuit pattern 39 consisting of an electroless copper plating layer 35 and an electrolytic copper plating layer 36 is formed through the electrolytic copper plating layer 36 in the through hole 34. There is. Furthermore, by etching and removing the metal plate of the support plate 31, a single-sided build-up type pudding plate 5 can be formed.

このようなプリント基板を形成するには第2図(a)に
示すように第1層の発泡弗素樹脂33の両面に第2図Φ
)のようにポリイミドのような熱硬化性樹脂32をロー
ラーコータ等を用いて塗布後、第2図(C)に示すよう
にパンチング加工法を用いてスルーボール34を開口後
、第2図(d)に示すように支持板31に加圧、加熱接
着する。
To form such a printed circuit board, as shown in FIG. 2(a), the second layer of Φ
) After applying a thermosetting resin 32 such as polyimide using a roller coater or the like, and opening the through ball 34 using a punching process as shown in FIG. 2(C), As shown in d), it is bonded to the support plate 31 under pressure and heat.

次いで第2図(e)に示すようにスルーホール34内に
電解銅メツキ層36を形成後、発泡弗素樹脂層33上に
無電解銅メツキN35を形成する。更に第2図(「)に
示すように該無電解銅メツキ層35上にレジストパター
ン41をホトリソグラフィ法で形成後、該レジストパタ
ーン41をマスクとして電解銅メツキ層36を形成する
Next, as shown in FIG. 2(e), after forming an electrolytic copper plating layer 36 in the through hole 34, an electroless copper plating layer N35 is formed on the foamed fluororesin layer 33. Further, as shown in FIG. 2(), a resist pattern 41 is formed on the electroless copper plating layer 35 by photolithography, and then an electrolytic copper plating layer 36 is formed using the resist pattern 41 as a mask.

更に第2図((至)に示すようにレジストパターン41
を除去して第1Nの発泡弗素樹脂層33上に無電解銅メ
ツキ層35と電解銅メツキ層36よりなる電源回路パタ
ーン37を形成後、第2図Q−1)に示すようにスルー
ホール34を形成し、両面に熱硬化性樹脂32が塗布形
成された第2層の発泡弗素樹脂層38を加圧、加熱積層
して形成し、前記工程を繰り返して前記した第2図(i
)に示す片面ビルドアップの多層プリント基板を形成す
る。
Furthermore, as shown in FIG.
After forming a power circuit pattern 37 consisting of an electroless copper plating layer 35 and an electrolytic copper plating layer 36 on the 1N foamed fluororesin layer 33 by removing the A second foamed fluororesin layer 38 having a thermosetting resin 32 coated on both sides is laminated under pressure and heat.
) A single-sided build-up multilayer printed circuit board is formed.

本発明の多層プリント基板の第2実施例を第3図(j)
に示す。本実施例はビルドアップ型多層プリントの基板
の両面ビルドアップ型構造の断面図である。
A second embodiment of the multilayer printed circuit board of the present invention is shown in FIG. 3(j).
Shown below. This embodiment is a cross-sectional view of a double-sided build-up type structure of a built-up type multilayer printed circuit board.

図示するように中間層51と絶縁層52が加圧積層され
たプリント基板54にはスルーホールランドパターン5
3が形成され、該ランドパターン53の上下のランドパ
ターン53A 、 53B上には、前記した両面に熱硬
化性樹脂層32を塗布した第1層の発泡弗素樹脂層33
が形成され、該樹脂層33に形成されたスルーホール3
4には電解銅メツキ層36が形成され、上下のランドパ
ターン53A 、 53Bと接続されている。
As shown in the figure, a through-hole land pattern 5 is provided on a printed circuit board 54 on which an intermediate layer 51 and an insulating layer 52 are laminated under pressure.
3 is formed, and on the land patterns 53A and 53B above and below the land pattern 53, the first foamed fluororesin layer 33 is coated with the thermosetting resin layer 32 on both sides.
is formed, and the through hole 3 formed in the resin layer 33
4 is formed with an electrolytic copper plating layer 36, which is connected to the upper and lower land patterns 53A and 53B.

また第1層の発泡弗素樹脂層33上に無電解メツキ層3
5と電解メツキ層36よりなる電源回路パターン37が
所定のパターンで形成されている。更にその上には第2
層の発泡弗素樹脂層38が形成され、該弗素樹脂層38
の両面には熱硬化性樹脂層32が塗布され、更にスルー
ホール34が形成されている。
Further, an electroless plating layer 3 is formed on the first layer of foamed fluororesin layer 33.
A power circuit pattern 37 is formed in a predetermined pattern. Furthermore, there is a second
A foamed fluororesin layer 38 of the layer is formed, and the fluororesin layer 38
A thermosetting resin layer 32 is coated on both sides of the plate, and a through hole 34 is further formed.

第2実施例の多層プリント基板の形成方法に付いて述べ
ると第3図(a)に示すように第1層の発泡弗素樹脂層
33の両面に第3図(b)に示すように熱硬化性樹脂3
2を塗布後、パンチング加工等により第2図(C)に示
すようにスルーボール34を形成する。
Regarding the method of forming the multilayer printed circuit board of the second embodiment, as shown in FIG. 3(a), both sides of the first foamed fluororesin layer 33 are thermally cured as shown in FIG. 3(b). Resin 3
2, a through ball 34 is formed by punching or the like as shown in FIG. 2(C).

次いで第3図(d)に示すようにプリント基板54の上
部のスルーホールランドパターン53A上に前記第1層
の発泡弗素樹脂層33のスルーホール34を合致させる
。この場合、図示しないがプリント基板の下側のランド
パターン53Bにも前記した第1層の発泡弗素樹脂層3
3のスルーボール34を合致させる。尚、第3図(d)
以陣の工程ではプリント基板の下側のスルーホールラン
ドパターン上にも同様の操作を施す。更に第3図(e)
に示すように、スルーホール34内、および発泡弗素樹
脂層33上に無電解メツキ層35を形成する。
Next, as shown in FIG. 3(d), the through holes 34 of the first foamed fluororesin layer 33 are aligned with the through hole land pattern 53A on the upper part of the printed circuit board 54. In this case, although not shown, the first layer of the foamed fluororesin layer 3 described above is also included in the land pattern 53B on the lower side of the printed circuit board.
Match the through ball 34 of No. 3. Furthermore, Fig. 3(d)
In the next step, the same operation is performed on the through-hole land pattern on the bottom of the printed circuit board. Furthermore, Fig. 3(e)
As shown in FIG. 3, an electroless plating layer 35 is formed inside the through hole 34 and on the foamed fluororesin layer 33.

次いで第3図(f)に示すように発泡弗素樹脂層33上
にレジストパターン41を形成後、該レジストパターン
をマスクとして電解銅メツキ層36をスルーホール34
内および弗素樹脂層33上に所定のパターンで形成する
。更に第3図(ロ)に示すように、レジストパターン4
1を除去して第1層発泡弗素樹脂層33上に無電解銅メ
ツキ層35と電解銅メツキ層36より成る電源回路パタ
ーン37を形成する。
Next, as shown in FIG. 3(f), after forming a resist pattern 41 on the foamed fluororesin layer 33, the electrolytic copper plating layer 36 is formed into the through hole 34 using the resist pattern as a mask.
A predetermined pattern is formed inside and on the fluororesin layer 33. Furthermore, as shown in FIG. 3(b), a resist pattern 4 is formed.
1 is removed, and a power circuit pattern 37 consisting of an electroless copper plating layer 35 and an electrolytic copper plating layer 36 is formed on the first foamed fluororesin layer 33.

更に第3図(h)に示すように、電源回路パターン37
上に両面に熱硬化性樹脂層32を塗布し、スルーホール
34を設けた第2層の発泡弗素樹脂層38を加圧加熱積
層する。更に第3図0)に示すように、前記スルーホー
ル34内に無電解メツキ層35を形成後、第2層の発泡
弗素樹脂層38上に無電解銅メツキ層35と電解銅メツ
キ層36よりなる信号回路パターン39を形成し、第3
図(j)に示す構造を形成する。
Furthermore, as shown in FIG. 3(h), a power supply circuit pattern 37 is formed.
A thermosetting resin layer 32 is applied on both sides, and a second foamed fluororesin layer 38 provided with through holes 34 is laminated under pressure and heat. Furthermore, as shown in FIG. 30), after forming the electroless plating layer 35 in the through hole 34, the electroless copper plating layer 35 and the electrolytic copper plating layer 36 are formed on the second layer of foamed fluororesin layer 38. A signal circuit pattern 39 is formed, and a third signal circuit pattern 39 is formed.
A structure shown in figure (j) is formed.

本発明のビルドアップ型の多層プリント基板の第3実施
例の+r4造を第4図(d)に示す。図示するように本
実施例ではプリント基板54に設けたスルーホール34
内に例えば熱硬化性樹脂55が充填された構造で、この
構造により該スルーホール34の直上にスルーホールラ
ンドパターン56が形成でき、第2実施例のランドパタ
ーンに比して微細パターンが形成できる。
FIG. 4(d) shows a +r4 construction of a third embodiment of the build-up type multilayer printed circuit board of the present invention. As shown in the figure, in this embodiment, a through hole 34 provided in a printed circuit board 54
The through-hole land pattern 56 can be formed directly above the through-hole 34, and a finer pattern can be formed than the land pattern of the second embodiment. .

更にこのランドパターン56の直上に両面に熱硬化性樹
脂層32が塗布された第1層の発泡弗素樹脂層33のス
ルーホール34が当接するように加圧加熱積層され、該
スルーホール34の内部に電解メツキ層36が形成され
ている。上記第1層の発泡弗素樹脂層33上に無電解メ
ツキ層35と電解メツキ層36より成る電源回路パター
ン37が形成されその上にはスルーホール34内に電解
メツキ層36を形成し、両面に熱硬化性樹脂層32を形
成した第2層の発泡弗素樹脂層38が加圧積層されてい
る。
Further, the first layer of foamed fluororesin layer 33, which has a thermosetting resin layer 32 coated on both sides, is laminated under pressure and heat so that the through holes 34 of the first layer are in contact with each other directly above the land pattern 56, and the inside of the through hole 34 is heated and laminated. An electrolytic plating layer 36 is formed on the surface. A power circuit pattern 37 consisting of an electroless plating layer 35 and an electrolytic plating layer 36 is formed on the first foamed fluororesin layer 33, and an electrolytic plating layer 36 is formed in the through hole 34 on both sides. A second foamed fluororesin layer 38 on which the thermosetting resin layer 32 is formed is laminated under pressure.

このような多層プリント基板を形成するには、第4図(
a)に示すように中間層51とポリイミド樹脂よりなる
絶縁層52を加熱加圧形成したプリント基+)i54に
スルーホール34を形成し、該スルーホール34内に無
電解銅メツキ層35を形成後、該スルーホール34内に
粉末状のポリイミド樹脂55を充填した後、加熱溶融し
て樹脂を溶融後、冷却して硬化させる。
In order to form such a multilayer printed circuit board, the steps shown in Fig. 4 (
As shown in a), a printed base in which an intermediate layer 51 and an insulating layer 52 made of polyimide resin are formed under heat and pressure +) A through hole 34 is formed in i54, and an electroless copper plating layer 35 is formed in the through hole 34. After that, the through hole 34 is filled with powdered polyimide resin 55, heated and melted to melt the resin, and then cooled and hardened.

次いで第4図(b)に示すようにプリント基板54の両
面に無電解銅メツキ層+電解銅メツキ層35Aを形成す
る。更に第4図(C)に示すように基板54の上部にス
ルーホールランドパターン56を形成後、基板54の底
部にレジスト膜59を形成する。次いで第4図(d)に
示すように基板54の上部のスルーホールランドパター
ン56上に第1層の発泡弗素樹脂層33のスルーホール
34と合致させて積層する。ビルドアップ後、レジスト
膜59を除去して第4図(ロ)に示すプリント基板54
底部のスルーホールランドパターン56を形成する。
Next, as shown in FIG. 4(b), an electroless copper plating layer and an electrolytic copper plating layer 35A are formed on both sides of the printed circuit board 54. Furthermore, as shown in FIG. 4(C), a through-hole land pattern 56 is formed on the top of the substrate 54, and then a resist film 59 is formed on the bottom of the substrate 54. Next, as shown in FIG. 4(d), it is laminated on the through-hole land pattern 56 on the upper part of the substrate 54 so as to match the through-holes 34 of the first layer of foamed fluororesin layer 33. After build-up, the resist film 59 is removed to form a printed circuit board 54 as shown in FIG. 4(b).
A bottom through-hole land pattern 56 is formed.

本発明のビルドアップ型多層プリント基板の第4実施例
の構造を第5図(d)に示す。
The structure of a fourth embodiment of the build-up type multilayer printed circuit board of the present invention is shown in FIG. 5(d).

図示するように中間層51とポリイミド樹脂より成る絶
縁層52を加圧加熱積層したプリント基板54の底部に
はレジスト膜59が形成され、該プリント基板54の上
部スルーホールランドパターン53A上に、両面に熱硬
化性樹脂層32を塗布した第1層の発泡弗素樹脂層33
のスルーホール34が合致するように積層され、このス
ルーホール34内に電解銅メツキ層36が形成されてい
る。更に該第1層の発泡弗素樹脂層33上に無電解銅メ
ツキ層35と電解銅メツキ層36よりなる電源回路パタ
ーン37が形成され、該電源回路パターン37上にスル
ーホール34内に電解メツキ層36が形成された第2層
の発泡弗素樹脂層38が加圧、加熱積層されている。
As shown in the figure, a resist film 59 is formed on the bottom of a printed circuit board 54 in which an intermediate layer 51 and an insulating layer 52 made of polyimide resin are laminated under pressure and heat. A first foamed fluororesin layer 33 coated with a thermosetting resin layer 32
The through holes 34 are stacked so that they match, and an electrolytic copper plating layer 36 is formed in the through holes 34. Further, a power circuit pattern 37 consisting of an electroless copper plating layer 35 and an electrolytic copper plating layer 36 is formed on the first layer of foamed fluororesin layer 33, and an electrolytic plating layer is formed in the through hole 34 on the power circuit pattern 37. The second foamed fluororesin layer 38 on which 36 is formed is laminated under pressure and heat.

このような多層プリン)i板を形成するには、第5図(
a)に示すように、中間層51と絶縁層52を加圧加熱
積層したプリント基板54にスルーホール61を形成後
、該スルーホール61内も含めてプリント基板の表面に
無電解銅メツキ層と電解銅メツキ層の二層構造のパネル
メッキ層を形成する。
To form such a multilayer pudding) plate, the process shown in Fig. 5 (
As shown in a), after forming a through hole 61 in a printed circuit board 54 in which an intermediate layer 51 and an insulating layer 52 are laminated under pressure and heat, an electroless copper plating layer is formed on the surface of the printed circuit board including the inside of the through hole 61. A panel plating layer with a two-layer structure of electrolytic copper plating layer is formed.

次いで第5図(ロ)に示すように該プリント基板54の
底部にレジスト膜59を形成後、該プリント基板54の
上部に所定パターンのレジスト膜59を形成する。更に
第5図(C)に示すようにレジスト1959をマスクと
してパネルメッキ層をエツチングしてスルーホールラン
ドパターン53Aを形成後、該スルーホールランドパタ
ーン53A上に前記した第1層発泡弗素樹脂層33のス
ルーホール34が合致するように樹脂層33を加圧加熱
接着する。
Next, as shown in FIG. 5(B), a resist film 59 is formed on the bottom of the printed circuit board 54, and then a resist film 59 of a predetermined pattern is formed on the upper part of the printed circuit board 54. Further, as shown in FIG. 5(C), the panel plating layer is etched using the resist 1959 as a mask to form a through-hole land pattern 53A, and then the above-described first foamed fluororesin layer 33 is formed on the through-hole land pattern 53A. The resin layer 33 is bonded under pressure and heat so that the through holes 34 of the two are aligned with each other.

このような第1実施例より第4実施例に述べたビルドア
ップ型構造のプリント基板によれば、熱硬化性樹脂に金
属パターンの厚さ方向の寸法が発泡弗素樹脂に塗布して
積層時に溶融した熱硬化性樹脂に埋めこまれた形となり
、平坦な多層プリント基板が得られる。更に発泡弗素樹
脂の表面は空気を多く含んだ多孔性であるので、従来の
ようにスパッタ法によらずとも無電解メツキ法等の化学
メツキ法で容易に金属パターンが形成できる。
According to the built-up type printed circuit boards described in the first to fourth embodiments, the dimension in the thickness direction of the metal pattern on the thermosetting resin is applied to the foamed fluororesin and melted during lamination. This results in a flat multilayer printed circuit board that is embedded in thermosetting resin. Furthermore, since the surface of the foamed fluororesin is porous and contains a large amount of air, a metal pattern can be easily formed by a chemical plating method such as an electroless plating method instead of the conventional sputtering method.

また従来、プリプレグにガラス布に弗素樹脂を含浸させ
たものを使用しているが、加熱加圧して接着する温度が
高くなるため、ベース基板にガラスエポキシ樹脂のよう
な有機材料の基板が用いることが出来かったが、本実施
例では接着温度が熱硬化性樹脂の硬化温度170〜20
0°Cで済むため、有機材料の基板が使用できる。また
誘電率が低下するため、信号の高速伝送が図れる。
Conventionally, prepreg is made of glass cloth impregnated with fluororesin, but since the temperature of heating and pressurizing the adhesive is high, it is recommended to use an organic material such as glass epoxy resin as the base substrate. However, in this example, the bonding temperature was the curing temperature of the thermosetting resin, 170 to 20
Since the temperature is 0°C, an organic material substrate can be used. Furthermore, since the dielectric constant is lowered, high-speed signal transmission can be achieved.

また本発明のプリプレグは、弾性率が小さく、加圧、加
熱成形時に応力の発生が少ないため、ベース基板として
セラミック、或いはガラスエポキシ樹脂のような有機、
無機の材料が使用でき、更に気泡を多数含有しているの
で加圧、加熱成形時の接着強度が向上する。
In addition, the prepreg of the present invention has a small elastic modulus and generates little stress during pressurization and heat molding, so it can be used as a base substrate of ceramics, organic materials such as glass epoxy resin, etc.
An inorganic material can be used, and since it contains a large number of bubbles, the adhesive strength during pressurization and heat molding is improved.

更に本発明の多層プリント基板の第5実施例に付いて述
べる。第6図(a)は本実施例の断面図、第6図(b)
は第6図(a)の要部拡大図で、信号を高速に伝送する
信号ペア層を電源グランド層でサンドインチしたストリ
ップライン構造の多層プリント基)反である。
Furthermore, a fifth embodiment of the multilayer printed circuit board of the present invention will be described. Figure 6(a) is a sectional view of this embodiment, Figure 6(b)
6(a) is an enlarged view of the main part of FIG. 6(a), which is the opposite of a multilayer printed circuit board with a stripline structure in which a signal pair layer for transmitting signals at high speed is sandwiched between a power supply ground layer.

第6図(a)に示すようにガラス布に弗素樹脂を含浸さ
せた基材71にストリップライン構造の信号ペア層72
と電源グランド層73が形成され、この信号ペア層72
と電源グランド層73の間に第6図(b)に示す発泡弗
素樹脂層74の両面に熱硬化性樹脂32を50μm程度
の厚さに塗布した接着層75が積層形成され、該接着層
75の表面に塗布された樹脂32が表面に滲み出して信
号ペア層72と電源グランド層73の金属パターンの厚
さ方向を埋める構造をとっている。
As shown in FIG. 6(a), a signal pair layer 72 with a strip line structure is formed on a base material 71 made of glass cloth impregnated with fluororesin.
A power ground layer 73 is formed, and this signal pair layer 72
An adhesive layer 75 is formed by applying thermosetting resin 32 to a thickness of about 50 μm on both sides of the foamed fluororesin layer 74 shown in FIG. The structure is such that the resin 32 applied to the surface oozes out to the surface and buries the metal patterns of the signal pair layer 72 and the power supply ground layer 73 in the thickness direction.

本実施例のプリント基板構造によれば、発泡弗素樹脂層
74を用いているため、内部に気泡が含有されているの
で、弗素樹脂本来の誘電率2.1より更に1.5の低誘
電率のプリプレグ層が得られ、形成されるプリント基板
の誘電率が大幅に低下し、信号の高速伝送が可能となる
According to the printed circuit board structure of this embodiment, since the foamed fluororesin layer 74 is used, air bubbles are contained inside, so the dielectric constant is lower than the original dielectric constant of fluororesin, which is 1.5, which is even lower than the original dielectric constant of 2.1. A prepreg layer is obtained, and the dielectric constant of the printed circuit board formed is significantly lowered, allowing high-speed signal transmission.

更に本発明の多層プリント基板の第6実施例′に付いて
述べる。第7図(a)は本実施例の断面図、第7図(b
)は第7図(a)の要部拡大図で、本実施例が第5実施
例と異なる点は、接着層76が発泡弗素樹脂層74に熱
硬化性樹脂32を含浸させた点にある。この発泡弗素樹
脂層74に熱硬化性樹脂32を含浸させる割合は、重量
%で発泡弗素樹脂74が40%の時に、熱硬化性樹脂3
2は60%の割合で混ぜるようにすると良い。熱硬化性
樹脂32の発泡弗素樹脂に対する含有量を増大させると
形成される接着層76の誘電率が増大し、熱硬化性樹脂
の含有量を低下させると、形成される接着層の熱膨張率
が増大するので、多層プリント基板に形成されるスルー
ホールの位置が変動しないような寸法安定性と、形成さ
れるプリント基板の誘電率の兼ね合いから熱硬化性樹脂
の含有量を60重量%とした場合が最適である。
Furthermore, a sixth embodiment of the multilayer printed circuit board of the present invention will be described. Fig. 7(a) is a sectional view of this embodiment, Fig. 7(b)
) is an enlarged view of the main part of FIG. 7(a). The difference between this embodiment and the fifth embodiment is that the adhesive layer 76 is formed by impregnating the foamed fluororesin layer 74 with the thermosetting resin 32. . The ratio of impregnating the thermosetting resin 32 into the foamed fluororesin layer 74 is such that when the foamed fluororesin 74 is 40% by weight, the thermosetting resin 3
It is best to mix 2 at a ratio of 60%. When the content of the thermosetting resin 32 relative to the foamed fluororesin increases, the dielectric constant of the adhesive layer 76 formed increases, and when the content of the thermosetting resin 32 decreases, the thermal expansion coefficient of the adhesive layer 76 increases. The thermosetting resin content was set at 60% by weight in order to balance the dimensional stability so that the position of the through hole formed in the multilayer printed circuit board would not change and the dielectric constant of the printed circuit board to be formed. The case is optimal.

更に本発明の多層プリント基板の第7実施例について述
べる。第8図(e)は本実施例の断面図、第8図(a)
より第8図(e)迄は本実施例のプリント基板の製造方
法を示す断面図である。
Furthermore, a seventh embodiment of the multilayer printed circuit board of the present invention will be described. FIG. 8(e) is a sectional view of this embodiment, FIG. 8(a)
8(e) are sectional views showing the method of manufacturing the printed circuit board of this embodiment.

第8図(e)に示すように本実施例の多層プリント基板
は、金属コアとなる厚さ0.5 mm程度の分厚い銅板
81の両面に発泡弗素樹脂、或いは発泡弗素樹脂に熱硬
化型樹脂を含浸させた低弾性体樹脂82が接着され、こ
れ等の銅板81とパターン形成用の銅箔83の間にガラ
スエポキシ樹脂、或いは本発明の発泡弗素樹脂に熱硬化
性樹脂を含浸させた接着層84が積層されて加熱加圧成
形された後、スルーホール85が形成されている。
As shown in FIG. 8(e), the multilayer printed circuit board of this embodiment has a thick copper plate 81 with a thickness of about 0.5 mm that serves as a metal core, and both sides are coated with foamed fluororesin, or foamed fluororesin and thermosetting resin. A glass epoxy resin or a foamed fluororesin of the present invention impregnated with a thermosetting resin is bonded between these copper plates 81 and copper foil 83 for pattern formation. After the layers 84 are laminated and heated and pressed, through holes 85 are formed.

このようなプリント基板を形成するには第8図(a)に
示すように厚さ0.5・鴫程度の分厚い銅+ff181
の両面に、第8図(b)に示すように発泡弗素樹脂、或
いは発泡弗素樹脂にポリイミドのような熱硬化性樹脂を
含浸させた低弾性樹脂82を加熱接着する。
To form such a printed circuit board, as shown in Fig. 8(a), thick copper with a thickness of about 0.5 cm + ff181 is used.
As shown in FIG. 8(b), a foamed fluororesin or a low-elasticity resin 82 made by impregnating a foamed fluororesin with a thermosetting resin such as polyimide is heat-bonded to both surfaces of the substrate.

次いで第8図(C)に示すようにパンチング加工法等を
用いてスルーホール86を形成し、次いで第8図(d)
に示すように、加工した銅板81と回路パターン形成用
の銅箔83の間に発泡弗素樹脂に熱硬化性樹脂を含浸さ
せた接着層84を積層後、加熱加圧成形後、第8図(e
)に示すようにスルーホール85を形成する。
Next, as shown in FIG. 8(C), a through hole 86 is formed using a punching method or the like, and then, as shown in FIG. 8(d).
As shown in FIG. e
), a through hole 85 is formed.

このように銅板81の両面に本発明の発泡弗素樹脂に熱
硬化性樹脂を含浸させた低弾性樹脂82を予め接着する
ことで、該樹脂82が接着強度が高いため、接着層84
を積層して加圧成形して一体化する際に該接着層84と
充分接着する。また本実施例の低弾性樹脂82は、従来
プリプレグとして使用しいるガラス繊維に弗素樹脂を含
浸させた樹脂に比して低弾性率であるため、スルーホー
ル85の形成時の積層板に掛かるストレスを該樹脂82
で吸収できるので、銅板81とその表面に接着した樹脂
82との間に歪が入らない状態でスルーホールが形成で
きるため、樹脂が銅板の表面より剥離する現象がなくな
り、スルーホールが高精度に加工できるため、メツキ液
が充分スルーホール内に入り込み、スルーホール内のメ
ツキネ良が防げる。
In this way, by bonding in advance the low elasticity resin 82, which is a foamed fluororesin of the present invention impregnated with a thermosetting resin, on both sides of the copper plate 81, the resin 82 has high adhesive strength, so that the adhesive layer 84
When they are laminated and pressure-molded to integrate, they are sufficiently adhered to the adhesive layer 84. Furthermore, the low modulus resin 82 of this embodiment has a lower modulus of elasticity than the resin conventionally used as prepreg, which is made by impregnating glass fiber with a fluororesin. The resin 82
Since the through-hole can be formed without strain between the copper plate 81 and the resin 82 bonded to its surface, the phenomenon of the resin peeling off from the surface of the copper plate is eliminated, and the through-hole can be formed with high precision. Since it can be machined, the plating liquid can sufficiently penetrate into the through-hole, preventing plating defects inside the through-hole.

〔発明の効果〕〔Effect of the invention〕

以上の説明から明らかなように本発明によれば、低誘電
率で平坦で製造が容易な多層プリント基板が得られる効
果がある。
As is clear from the above description, the present invention has the effect of providing a multilayer printed circuit board that has a low dielectric constant, is flat, and is easy to manufacture.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の多層プリント基板の原理図、第2図(
a)より第2図(1)迄は本発明の多層プリント基板の
第1実施例の製造工程図、 第3図(a)より第3図(j)は本発明の多層プリント
基板の第2実施例の製造工程図、 第4図(a)より第4図(d)迄は本発明の多層プリン
ト基板の第3実施例の製造工程図、 第5図(a)より第5図(d)迄は本発明の多層プリン
ト基板の第4実施例の製造工程図、 第6図(a)は本発明の多層プリント基板の第5実施例
の断面図、 第6図(b)は第6図(a)の要部拡大図、第7図(a
)は本発明の多層プリント基板の第6実施例の断面図、 第7図(b)は第7図(a)の要部拡大図、第8図(a
)より第8図に)迄は本発明の多層プリント基板の第7
実施例の製造工程図、 第9図は従来の多層プリント基板の構造を示す断面図、 第10図は従来の多層プリント基板の構造を示す断面図
、 第11図は従来の多層プリント基板の構造を示す断面図
である。 図に於いて、 31は支持板、32は熱硬化性樹脂、33は第1層発泡
弗素樹脂層、34,61.85.86はスルーホール、
35は無電解銅メツキ層、36は電解銅メツキ層、35
Aは無電解+電解銅メツキ層、37は電源回路パターン
、38は第2層発泡弗素樹脂層、39は信号回路パター
ン、51は中間層、52は絶縁層、53A、53B、5
6はスルーホールランドパターン、54はプリント基板
、55はポリイミド樹脂、57 、83は銅箔、58は
金属膜、59はレジスト膜、71は基材、72は信号ベ
ア層、73は電源グランド層、74は発泡弗素樹脂、?
5.76.84は接着層、81は銅板、82は低弾性体
樹脂、100は導体層、200は絶縁層を示す。 ノド湧卦e)4−多重7・グ)統1(召5のlPPb0
第1図 ζQ) (C)    34 シト尋い−ツシηう層7ソシL)k41し1づrr 呻
rシ櫓長B竺rPir5!J第2図 第 3 図 ノド発日9−づり1七−りきhl(版−才2突2唾リツ
お恨遣工オデCり゛第3図 (jl ントダとF!!/lづ札4t7・リンF靭=lンiz更
ざ始りシ墳5、ゴし頂Qり第3図 fIRT&57 7+1J=+し34        (55X”9イミ
rJt1月号+         tl 7発輌峠層71ハIf匈及声オ3笑埒例内鴨に壷エネi
図61スルネール 勺1 5 図 第 6 叉(Q) 第 7 図(Q) @箔、3゛c> 118  図
Figure 1 is a principle diagram of the multilayer printed circuit board of the present invention, and Figure 2 (
From a) to FIG. 2(1) are manufacturing process diagrams of the first embodiment of the multilayer printed circuit board of the present invention, and from FIG. 3(a) to FIG. 3(j) are the manufacturing process diagrams of the second embodiment of the multilayer printed circuit board of the present invention. Manufacturing process diagrams of the embodiment, Figures 4(a) to 4(d) are manufacturing process diagrams of the third embodiment of the multilayer printed circuit board of the present invention, and Figures 5(a) to 5(d). 6(a) is a sectional view of the fifth embodiment of the multilayer printed circuit board of the present invention, and FIG. 6(b) is a sectional view of the fourth embodiment of the multilayer printed circuit board of the present invention. An enlarged view of the main part of Figure (a), Figure 7 (a)
) is a sectional view of the sixth embodiment of the multilayer printed circuit board of the present invention, FIG. 7(b) is an enlarged view of the main part of FIG. 7(a), and FIG.
) to FIG.
Figure 9 is a cross-sectional view showing the structure of a conventional multilayer printed circuit board, Figure 10 is a cross-sectional view showing the structure of a conventional multilayer printed circuit board, and Figure 11 is a structure of a conventional multilayer printed circuit board. FIG. In the figure, 31 is a support plate, 32 is a thermosetting resin, 33 is a first foamed fluororesin layer, 34, 61, 85, 86 are through holes,
35 is an electroless copper plating layer, 36 is an electrolytic copper plating layer, 35
A is an electroless + electrolytic copper plating layer, 37 is a power circuit pattern, 38 is a second foamed fluororesin layer, 39 is a signal circuit pattern, 51 is an intermediate layer, 52 is an insulating layer, 53A, 53B, 5
6 is a through hole land pattern, 54 is a printed circuit board, 55 is polyimide resin, 57 and 83 are copper foils, 58 is a metal film, 59 is a resist film, 71 is a base material, 72 is a signal bare layer, 73 is a power ground layer , 74 is foamed fluororesin, ?
5, 76, and 84 are adhesive layers, 81 is a copper plate, 82 is a low elastic resin, 100 is a conductive layer, and 200 is an insulating layer. Throat spring trigram e) 4-Multiple 7/G) Tong 1 (Call 5 lPPb0
Figure 1 ζQ) (C) 34 Shito Hiroi-Tushi η U layer 7 Soshi L) k41 Shi1zurr Moaner Shitoarashicho BjirPir5! J fig.・Rin F toughness = lnniz Sarazagirishi tomb 5, goshitop Qri Figure 3fIRT&57 7+1J=+shi34 (55X”9 imirJtJanuary issue + tl 7shototoge layer 71haIf匈and Voice O3 Laughter
Figure 61 Surnaire 1 5 Figure 6 Fork (Q) Figure 7 (Q) @Foil, 3゛c> 118 Figure

Claims (3)

【特許請求の範囲】[Claims] (1)所定のパターンの導体層(100)と絶縁層(2
00)とを多層に有する多層プリント基板に於いて、前
記絶縁層(200)が熱硬化性樹脂(32)を塗布、或
いは含浸させたシート状の発泡弗素樹脂層(33,38
,74,76)よりなる接着層(75,76)であるこ
とを特徴とする多層プリント基板。
(1) Predetermined pattern of conductor layer (100) and insulating layer (2)
00) in a multilayer printed circuit board, the insulating layer (200) is a sheet-like foamed fluororesin layer (33, 38) coated with or impregnated with a thermosetting resin (32).
, 74, 76).
(2)電源グランド層(73)を形成した基材(71)
と信号配線ペア層(72)を形成した基材(71)の間
に前記熱硬化性樹脂(32)を塗布、或いは含浸させた
シート状の発泡弗素樹脂層(74)よりなる接着層(7
5)を有することを特徴とする請求項1記載の多層プリ
ント基板。
(2) Base material (71) on which a power ground layer (73) was formed
and a base material (71) on which a signal wiring pair layer (72) is formed, and an adhesive layer (7) consisting of a sheet-like foamed fluororesin layer (74) coated or impregnated with the thermosetting resin (32).
5) The multilayer printed circuit board according to claim 1, wherein the multilayer printed circuit board has the following features.
(3)発泡弗素樹脂層(82)、或いは発泡弗素樹脂層
に熱硬化型樹脂を含浸させた樹脂層よりなる接着層で内
層金属板(81)の両面を被覆し、該内層金属板(81
)の両面に前記接着層(84)を積層したことを特徴と
する請求項1記載の多層プリント基板。
(3) Both sides of the inner layer metal plate (81) are covered with an adhesive layer consisting of a foamed fluororesin layer (82) or a resin layer in which the foamed fluororesin layer is impregnated with a thermosetting resin.
2. The multilayer printed circuit board according to claim 1, wherein the adhesive layer (84) is laminated on both sides of the board.
JP13791988A 1988-06-03 1988-06-03 Multilayer printed board Pending JPH01307294A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13791988A JPH01307294A (en) 1988-06-03 1988-06-03 Multilayer printed board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13791988A JPH01307294A (en) 1988-06-03 1988-06-03 Multilayer printed board

Publications (1)

Publication Number Publication Date
JPH01307294A true JPH01307294A (en) 1989-12-12

Family

ID=15209751

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13791988A Pending JPH01307294A (en) 1988-06-03 1988-06-03 Multilayer printed board

Country Status (1)

Country Link
JP (1) JPH01307294A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1035164A (en) * 1996-04-25 1998-02-10 Samsung Aerospace Ind Ltd Ic card and manufacture thereof
US6351393B1 (en) 1999-07-02 2002-02-26 International Business Machines Corporation Electronic package for electronic components and method of making same
US6373717B1 (en) 1999-07-02 2002-04-16 International Business Machines Corporation Electronic package with high density interconnect layer
US6992896B2 (en) 2003-01-30 2006-01-31 Endicott Interconnect Technologies, Inc. Stacked chip electronic package having laminate carrier and method of making same
US7023707B2 (en) 2003-01-30 2006-04-04 Endicott Interconnect Technologies, Inc. Information handling system
US7161810B2 (en) 2003-01-30 2007-01-09 Endicott Interconnect Technologies, Inc. Stacked chip electronic package having laminate carrier and method of making same
US7332818B2 (en) 2005-05-12 2008-02-19 Endicott Interconnect Technologies, Inc. Multi-chip electronic package with reduced line skew and circuitized substrate for use therein
JP2009260402A (en) * 2009-08-12 2009-11-05 Tessera Interconnect Materials Inc Wiring circuit board, and manufacturing method thereof

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1035164A (en) * 1996-04-25 1998-02-10 Samsung Aerospace Ind Ltd Ic card and manufacture thereof
US6351393B1 (en) 1999-07-02 2002-02-26 International Business Machines Corporation Electronic package for electronic components and method of making same
US6373717B1 (en) 1999-07-02 2002-04-16 International Business Machines Corporation Electronic package with high density interconnect layer
US6829823B2 (en) 1999-07-02 2004-12-14 International Business Machines Corporation Method of making a multi-layered interconnect structure
US7024764B2 (en) 1999-07-02 2006-04-11 International Business Machines Corporation Method of making an electronic package
US6992896B2 (en) 2003-01-30 2006-01-31 Endicott Interconnect Technologies, Inc. Stacked chip electronic package having laminate carrier and method of making same
US7023707B2 (en) 2003-01-30 2006-04-04 Endicott Interconnect Technologies, Inc. Information handling system
US7035113B2 (en) 2003-01-30 2006-04-25 Endicott Interconnect Technologies, Inc. Multi-chip electronic package having laminate carrier and method of making same
US7161810B2 (en) 2003-01-30 2007-01-09 Endicott Interconnect Technologies, Inc. Stacked chip electronic package having laminate carrier and method of making same
US7665207B2 (en) 2003-01-30 2010-02-23 Endicott Interconnect Technologies, Inc. Method of making a multi-chip electronic package having laminate carrier
US7332818B2 (en) 2005-05-12 2008-02-19 Endicott Interconnect Technologies, Inc. Multi-chip electronic package with reduced line skew and circuitized substrate for use therein
JP2009260402A (en) * 2009-08-12 2009-11-05 Tessera Interconnect Materials Inc Wiring circuit board, and manufacturing method thereof

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