JPH01304750A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To facilitate transmission of signals inputted from external circuits with one type of integrated circuits even if a plurality of the amplitudes of the signal exist by a method wherein input buffers having a plurality of thresholds are provided for one input terminal and a circuit selecting one buffer from a group of the buffers are provided and the threshold of the input buffer is controlled by an external setting voltage. CONSTITUTION:An input terminal 1 is connected to input buffers 5 and 6 in common and the respective outputs of the input buffers 5 and 6 are inputted to an input signal selector 11. An input terminal 3 is connected to an input buffer 9 and the output of the input buffer 9 is inputted to the input selector 11 as a control signal 13. When the voltage of the input terminal 3 is set at a VDD level, the control signal 13 takes a high level and the signal from the input buffer 6 is made to be effective by the input signal selector 11 and transmitted to an internal circuit. To the contrary, when the voltage of the input terminal 3 is set a VSS level, the control signal 13 takes a low level and the signal from the input buffer 5 is made to be effective by the input signal selector 11 and transmitted to the internal circuit.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit, and particularly to a method for externally electrically controlling the threshold value of an input voltage detection circuit (hereinafter referred to as a manual buffer) of a semiconductor integrated circuit. Regarding circuit configuration.

[Conventional technology]

Conventionally, the threshold value of an input buffer of a semiconductor integrated circuit has been determined to be one type depending on the conditions specific to the process used or the circuit configuration. In a master slice type integrated circuit, by selecting and arranging input buffers with different circuit configurations for each input buffer, it is possible to realize an integrated circuit having input buffers with multiple threshold values, but the process that can be changed is It was limited to the integrated circuit manufacturing process.

[Problem to be solved by the invention]

The conventional semiconductor integrated circuit described above has a structure in which the input buffer has only one type of threshold value, or is fixed to one type for one input terminal at the integrated circuit manufacturing stage.
When there are multiple amplitudes of input signals to be connected to the outside, it is impossible or insufficient to transmit the signals using an input buffer with a single threshold value, so an integrated circuit with threshold values for multiple input buffers is prepared. Another disadvantage is that an amplitude conversion circuit must be externally connected to adjust the amplitude of the input signal to the threshold value of the input buffer of the integrated circuit.

[Means to solve the problem]

The semiconductor integrated circuit of the present invention includes an input buffer having a plurality of threshold values for − input terminals, a circuit for selecting one buffer from the buffer group, and an external terminal connected to the input buffer,
It has a control signal that controls which type of threshold value to set for the input buffer.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an input circuit section according to an embodiment of the present invention. Input terminal 1 is electrically commonly connected to input buffers 5 and 6, and the outputs of input buffers 5 and 6 are input to input signal selection circuit 11, respectively.

Input buffers 5 and 6 are input buffers having different input threshold values, and in this embodiment, VnD=5V.

As an input buffer of a CMO8 integrated circuit with V ss = OV, the input buffer 5 has a threshold value V th 1=1
/2 VDD (') CM OS level input buffer, input buffer 6 is TTL level input cover buffer with threshold value Vthz=4.5v. The input terminal 3 is connected to an input buffer 9, and the output of the input buffer 9 is inputted as a control signal 13 to an input signal selection circuit 11. When the input terminal 3 is set to VDD high level, the control signal 13 becomes high level, and the input signal selection circuit 11 selects the input buffer 6.
The signal becomes valid and is transmitted to the internal circuit. Conversely, when the input terminal 3 is set to the V'3B level, the control signal 13 becomes low level, and the selection circuit 11 makes the signal of the input buffer 5 valid and transmits it to the internal circuit.

As explained above, when input terminal 3 is at VDD high level, input terminal 1 is connected to input buffer 6. Input signal selection circuit 11
Since the signal is transmitted to the internal circuit via the input terminal, the threshold value of the input terminal can be operated as a TTL level buffer. On the other hand, when input terminal 3 is set to VS8 level, input terminal 1 becomes input buffer 5. Input signal selection circuit 11
The threshold value of input terminal 1 can be regarded as a CMOS level human buffer in operation.

Input terminal 2. Input buffers 7, 8. Input signal selection circuit 1
2, the input circuit consists of input terminal 4 as in the above explanation.
The threshold voltage of the input buffer can be controlled by setting the voltage of . It is also possible to commonly control a plurality of input signal selection circuits with one control signal, and to use a signal from an internal circuit as a control signal.

FIG. 2 is a circuit diagram of an input circuit section according to a second embodiment of the present invention. The names and connections of each part are the same as those in the previous embodiment, so they will be omitted. In the second embodiment, the circuit configuration of the input signal selection circuits 11.12 is such that two 3-state buffers with activation signal input terminals are arranged, and the level of the control signal 13.14 is input to the input signal selection circuits 11.12. The configuration is such that either one of the two signals is valid.

〔Effect of the invention〕

As explained above, the present invention includes input buffers with a plurality of threshold values for - input terminals, a circuit for selecting one buffer from the buffer group, and a circuit connected to an external terminal and a circuit for selecting one buffer from the buffer group. By having a control signal that controls which type of threshold is set, even if there are multiple amplitudes of externally input signals, signal transmission can be performed with one type of integrated circuit. This has the effect of eliminating the need for a switching circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an input circuit section of a semiconductor integrated circuit according to the present invention. FIG. 2 is a circuit diagram of the input circuit section of the semiconductor integrated circuit of the present invention. ■・・・Input terminal, 2・・・Input terminal, 3
...Input terminal, 4...Input terminal, 5.
...CMOS level manual buffer, 6...
・TTL level input buffer, 7...CMOS
Level human buffer, 8...TTL level human kabaka buffer...Input buffer, 10...
...Input buffer, 11...Input signal selection circuit, 12...Input signal selection circuit, 13...
- Control signal, 14... Control signal. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] In a semiconductor integrated circuit, a plurality of input voltage detection circuits with different threshold values are connected to an input terminal, an input signal selection circuit is configured to enable only one of the plurality of input voltage detection circuits, and an input signal selection circuit is connected to an external terminal and has a different threshold value. A semiconductor integrated circuit comprising a control signal that controls the state of a signal selection circuit.