JPH02131618A - Output buffer circuit - Google Patents

Output buffer circuit

Info

Publication number
JPH02131618A
JPH02131618A JP63286040A JP28604088A JPH02131618A JP H02131618 A JPH02131618 A JP H02131618A JP 63286040 A JP63286040 A JP 63286040A JP 28604088 A JP28604088 A JP 28604088A JP H02131618 A JPH02131618 A JP H02131618A
Authority
JP
Japan
Prior art keywords
circuit
input terminal
gate circuit
drive capability
output buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63286040A
Other languages
Japanese (ja)
Inventor
Kimihiro Ishitobi
Mitsuto Iketani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC AccessTechnica Ltd
Original Assignee
NEC Corp
NEC AccessTechnica Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC AccessTechnica Ltd filed Critical NEC Corp
Priority to JP63286040A priority Critical patent/JPH02131618A/en
Publication of JPH02131618A publication Critical patent/JPH02131618A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To obtain an optional drive capability by constituting the circuit with plural 3-state gate circuit whose drive capability differs connected in parallel between an input terminal and an output terminal and making the said gate circuit enable selectively based on a control signal.
CONSTITUTION: When a level '1' is inputted to an external input terminal 15, a 3-state gate circuit 13 is enabled and a 3-state gate circuit 14 is disabled. Thus, only the circuit 13 is connected substantially between the input terminal 11 and an external output terminal 12 and an output buffer circuit having a drive capability depending on the gate circuit 13 is obtained. On the other hand, when a '0' is inputted to the external input terminal 15, the circuit is disabled and the circuit 14 is enabled. Thus, only the circuit 14 is connected substantially between the input terminal 11 and the external output terminal 12 and the output buffer circuit with the drive capability decided by the gate circuit 14 is obtained.
COPYRIGHT: (C)1990,JPO&Japio
JP63286040A 1988-11-11 1988-11-11 Output buffer circuit Pending JPH02131618A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63286040A JPH02131618A (en) 1988-11-11 1988-11-11 Output buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63286040A JPH02131618A (en) 1988-11-11 1988-11-11 Output buffer circuit

Publications (1)

Publication Number Publication Date
JPH02131618A true JPH02131618A (en) 1990-05-21

Family

ID=17699192

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63286040A Pending JPH02131618A (en) 1988-11-11 1988-11-11 Output buffer circuit

Country Status (1)

Country Link
JP (1) JPH02131618A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002076874A (en) * 2000-08-28 2002-03-15 Nec Kyushu Ltd Output interface circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002076874A (en) * 2000-08-28 2002-03-15 Nec Kyushu Ltd Output interface circuit

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