JPH02131618A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To obtain an optional drive capability by constituting the circuit with plural 3-state gate circuit whose drive capability differs connected in parallel between an input terminal and an output terminal and making the said gate circuit enable selectively based on a control signal. CONSTITUTION:When a level '1' is inputted to an external input terminal 15, a 3-state gate circuit 13 is enabled and a 3-state gate circuit 14 is disabled. Thus, only the circuit 13 is connected substantially between the input terminal 11 and an external output terminal 12 and an output buffer circuit having a drive capability depending on the gate circuit 13 is obtained. On the other hand, when a '0' is inputted to the external input terminal 15, the circuit is disabled and the circuit 14 is enabled. Thus, only the circuit 14 is connected substantially between the input terminal 11 and the external output terminal 12 and the output buffer circuit with the drive capability decided by the gate circuit 14 is obtained.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an output buffer circuit configured in the output stage of a semiconductor integrated circuit, and in particular to an output buffer circuit suitable for driving various loads of different sizes. Regarding circuits. [Prior Art] Conventionally, an output buffer circuit provided in an output stage of a semiconductor integrated circuit has a gate circuit 33 connected between an input terminal 31 and an external output terminal 32, as shown in FIG. It was something like that. The drive capacity of the gate circuit 33 was determined by assuming the usage conditions of the load at the time of design. [Problems to be Solved by the Invention] However, in the conventional output buffer circuit configured as described above, inconveniences occur when the load size differs from the value assumed at the time of design, and when various loads The disadvantage was that it lacked flexibility when driving. The present invention has been made in view of such problems, and includes:
An object of the present invention is to provide an output buffer circuit whose driving capability can be switched.

[Means for Solving the Problems] The output buffer circuit according to the present invention is composed of a plurality of three-state gate circuits having different driving capacities and connected in parallel between an input terminal and an output terminal. One of the plurality of three-state gate circuits is selectively enabled based on a control signal. [Operation] According to the present invention, among the plurality of three-state gate circuits connected in parallel between the input terminal and the output terminal, only the three-state gate circuit selected by the control signal is in the enabled state, and the other three are in the enabled state. Since the state gate circuit is in a disabled state (high impedance), only the selected 3-state gate circuit is connected between the input and output terminals. Since multiple 3-state gate circuits have different driving capabilities, any 3-state gate circuit can be set to any 3-state gate circuit depending on the control signal.
By enabling the state gate circuit, any drive capability can be obtained. [Example] Next, an example of the present invention will be described with reference to the attached drawings. FIG. 1 is a diagram showing an output buffer circuit according to an embodiment of the present invention. Between the input terminal 11 to which the output of the internal circuit (not shown) of the semiconductor integrated circuit is given, and the external output terminal 12, there is a
Two three-state gate circuits 13 and 14 are connected in parallel. These three-state gate circuits 13 and 14 have different driving capacities. When the 3-state gate circuit 13 receives the control signal "1" and the 3-state gate circuit 14 receives the control signal "0", it enters an enabled state, and when the control signals have other values, the circuit enters a disabled state. ．． This control signal is given from an external terminal 15. According to such a configuration, when "1" is input to the external input terminal 15, the 3-state gate circuit 13 is enabled and the 3-state gate circuit 14 is disabled, so that the input terminal 11 and the external output terminal 12 are connected to each other. In between, only the 3-state gate circuit 13 is substantially connected, and this gate circuit 1
An output buffer circuit with a driving capacity determined in step 3 is obtained. On the other hand, when "0" is input to the external input terminal 15, the 3-state gate circuit 13 is disabled and the 3-state gate circuit 14 is enabled. Only the 3-state gate circuit 14 is connected to the 3-state gate circuit 14, and an output buffer circuit with a driving capacity determined by the gate circuit 14 is obtained. In this way, according to the present circuit, the two driving capacities can be switched by the control signal from the external input terminal 15. Figure 2 shows another embodiment of the invention. Between the input terminal 21 and the external output terminal 22, there are four terminals with different driving capacities.
State gate circuits 23, 24, 25, and 26 are connected in parallel. External input terminals 27 and 28 are connected to input terminals A and B of a 2-4 decoder 29, respectively. 2-4
The decoder 29 sets the output of one of Yo, Y 1 r Y2 + y3 to "O" according to the pinary data of input terminals A and B. These outputs Yo to Y3 are 3
It is given as a control signal for state gate circuits 23, 24, 25, and 26. According to this circuit, four 3-state gate circuits 23 are connected by 2-bit data to external input terminals 27 and 28.
Since one of the gate circuits 23 to 26 is selectively enabled, the desired drive capability is obtained by selecting one of the gate circuits 23 to 26 as a 3-state gate circuit corresponding to the required drive capability. be able to. In the above embodiments, the control signal is input from the outside, but it is also possible to detect an increase or decrease in the current flowing through the load and adaptively switch the drive capacity according to the result. [Effects of the Invention] As explained above, since the present invention is configured to select a plurality of three-state gate circuits with different driving capacities using a control signal, it is possible to obtain an output buffer circuit whose driving capacities can be switched. This has the effect of being able to flexibly respond to load conditions.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an output buffer circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram of an output buffer circuit according to another embodiment of the present invention, and FIG. 3 is a circuit diagram of a conventional output buffer circuit. It is. 11, 21, 31. Input terminals, 12, 22, 32; External output terminals, 13, 14. 23 to 26; 3-state gate circuit, 1 5. 27, 28; External input terminal, 29: 2-4 decoder, 33; Gate circuit

Claims (1)

[Claims] (1) A plurality of 3-state gate circuits with different driving capacities are connected in parallel between an input terminal and an output terminal, and one of them is selectively enabled based on a control signal. Features an output buffer circuit.